Exactly ten years ago I was helping Adaptive Silicon, a start-up, with their European marketing. The company had a great pedigree, with roots in National Semiconductor and financial and process support from LSI Logic and financial and tools support from Synplicity. (For new readers – LSI Logic is now LSI Corporation and is no longer an ASIC company, as it was then. Synplicity was an independent company supplying EDA tools for FPGAs and is now part of Synopsys.)
The product was an FPGA technology for integration into ASICs and SoCs. The idea was that, within the design, small blocks of FPGA fabric would provide significant flexibility. For example, by adding programmability, it should be possible to fine-tune the design without a re-spin. The same properties would allow a basic design to be programmed to make different members of the same family by changing features in the FPGA area. One use that was particularly attractive was for a product being developed to meet a standard that was not yet finalised: the logic for the standard could be implemented in the FPGA and then field-upgraded when the standard was ratified.
The idea was good. Unfortunately there were several practical issues. The FPGA fabric was big: each gate-equivalent occupied the silicon area of around twenty ASIC gates. The fabric was slow: the system clock was rated at between 50- and 100-MHz, while the ASIC system clock was rated at 400-MHz. And the fabric wasn’t exactly power efficient. While these may have been the transitory problems of an emerging technology, the worst fault was timing. Ten years ago, the hot air was screaming out of the dot-com balloon, and every technology company was feeling the pain. In particular, investors were reluctant to continue funding many start-ups, even if they were a million miles away from the net. The final straw for Adaptive was when LSI pulled its “Liquid Silicon” ASIC product approach, effectively leaving the company without a major customer and backer.
Today the need for flexibility within an ASIC or SoC hasn’t gone away. To be able to fine-tune elements of a design is still an exciting prospect. To produce several members of a family from the same silicon is still a profitable approach. Producing products before standards are ratified is still a necessity of commercial life. And FPGA fabric still lags logic in density, speed and power.
A company based near York, in Northern England, has an alternative approach. Akya has created a dynamically-reconfigurable technology that the company is calling ART, which it is supplying as IP and supporting with design tools.
The building block is a Reconfigurable Processing Matrix (RPM). This has one or many processing elements, which are supported by an interconnect sequencer, instruction memory, reconfigurable interconnect, and an interface controller. RPMs are assembled into an ART core, through direct interconnections, with an ART Token Ring network controller. A core will also have shared memory and a master controller to control the core configuration.
The connectivity within the RPM is defined through the ART Architecture Description Language (ADL), and the functionality is defined in the ART Assembly Language (AAL). ADL is a simplified hardware description language, with features added to express the variable connectivity in the RPM. AAL is like a standard assembly language, again with added features, this time to define dynamic connectivity between blocks. An AAL programme is small – with only a few tens of lines of code, up to a few hundred.
Akya is also developing an ESL/C programming approach with “a major tools vendor,” and a C Compiler for developing the firmware will soon be available from a third party.
Within ART there is a clear separation between data paths and control paths. And if we are now beginning to sound as though we are describing a new processor architecture, this is one way in which one can define ART: by saying how it is like/unlike existing processor architectures. For example ART is a series of function units, like a VLIW processor. But VLIW implementations have a fixed microarchitecture, with limited operations and complex caches, and most have fixed memory data access schemes. In contrast, ART is flexible, RPMs have multiple functions, the memory system is predictable, avoiding the need for caches, and the memory architecture is flexible, matching bandwidth to required performance. Similar comparisons can be made with other architectures.
It is possible to create an entire ASIC with ART, but Akya expects that it will normally be used within SoCs and ASSPs to provide flexibility and in-use re-configurability. The company claims that ART is comparable to hard-wired RTL in silicon area: depending on the application and implementation, a typical application may be between 10% and 50% larger than an RTL solution, but, depending on the application, it may even turn out to be smaller. ART is comparable in power consumption, is low cost, and is flexible.
Creating a new design in ART is made easier and faster by exploiting the separation between the data path and the control flow: the data path is designed using ADL and then synthesised and sent to the back-end layout, timing analysis, etc. In parallel, the firmware is designed with AAL or a C complier and then run on ARTSim, a System-C model of the hardware, which Akya says is cycle accurate. As the firmware is developed, it can easily be modified to fix bugs or to meet requirements changes, without any need to touch the hardware, let alone carry out a multi-million-dollar re-spin. Changing the firmware can take place during development, to optimise the design; after manufacturing, to create variant members of the same family; and in the field, to meet changing standards or to add new features.
The next step is clearly integrating the Akya segment into a larger design, and this is where the new Cadence System Realization Alliance comes in. This is part of Cadence’s push to improve the overall approaches to developing systems, recognising that software and integration are as much a part of the design flow as purely creating transistors in silicon. The keystone of the alliance is an agreement for closer cooperation between Cadence and ARM, with the aim of making it easier to create devices with ARM cores and using the AMBA CoreLink to link SoC elements together. (There has been a lot of talk about creating IP blocks with an AMBA interface and then hooking them together on a bus. While this may be more inefficient in silicon, the overhead could be small compared with how much easier, faster and so cheaper it will be to integrate IP in a SoC.)
Included in the System Realization Alliance is a raft of other companies, including big names such as TSMC and Wind River, as well as smaller design consultancies and companies supplying IP, modelling environments and verification tools. The intention is to create an ecosystem that will operate at the system level for overall design of products.
That Akya is included in this Alliance will be a considerable boost to raising its profile. It will also make it easier for users to add dynamically reconfigurable technology to a design, since ART will fit nicely into the Cadence tool flow. It is probably going too far to say that it is an endorsement of the technology by Cadence, but, at the very least, it is unlikely that Cadence would get involved with a company whose technology did not have a role to play in pushing forward the Cadence vision.
A slightly different announcement involving ARM and TSMC intrigued me. As well as both being part of Cadence’s System Realization Alliance, they have just signed a deal that gives TSMC access to ARM Cortex and other processors and the CoreLink interconnect fabric, to be optimised on 28nm and 20nm processes. The public reason for this is that it makes it easier for SoC designers using ARM and targeting TSMC: they will have the confidence that they will get efficient silicon. But if you subscribe to the theory (set out by Bryon Moyer a few weeks ago) that, over time, foundries will move from pure-play to offering more tools and services, this is a nice chunk of stuff to have in the tool box.
Normally the world is ramping down in July. This year there are all sorts of interesting things happening.