Oslo, Norway, July 19th, 2010 – Energy Micro®, the energy friendly microcontroller company, has announced details of its EFM®32 Giant Gecko microcontroller product family.  For energy sensitive applications with high memory requirements, the 32-bit Giant Gecko (GG) will provide Flash configurations up to 1024KB with the added option of embedded USB connectivity.

There will be 48 EFM32GG microcontrollers offering a choice of 64, 128, 256, 512 and 1024 KB Flash memory blocks and a RAM of 32KB or 128KB.  The microcontrollers’ pin and software compatibility with the existing Gecko product family means designers can develop products using the existing Gecko microcontroller and migrate to Giant Gecko when the higher memory parts enter production.  Package options will include QFN64, QFP100 and BGA112.

Built around the energy-efficient ARM® Cortex(TM)-M3 processor architecture, the Giant Gecko, Gecko and Tiny Gecko microcontrollers demonstrate an energy usage a quarter of that of alternative 8-, 16- or 32-bit microcontrollers.  With a wake-up time of just 2µs and current consumption of 180µA per MHz executing code from Flash, 900nA in deep sleep mode and 20nA in shut off mode, the microcontrollers are proven capable of extending typical battery life by 300%.

The Giant Gecko’s embedded USB connectivity option will be USB2.0 compliant at full speed (12Mbit/s), integrating 2KB endpoint buffers and handling up to 10 endpoints.  It will provide support for USB host and on-the-go configurations as well as bootloader over USB.  Additional extended communication options offered by Giant Gecko will include dual I2C and up to 5 USART/UART serial interfaces.

Giant Gecko will feature the same selection of energy-saving peripherals as the companion Gecko and Tiny Gecko products.  These include: an 8-channel, 12-bit ADC using 200µA at full resolution and 1Msamples/sec conversion rate, a 4×40 segment LCD controller using 900nA and a special Low Energy UART consuming just 100nA at 9600baud.  In addition, for wireless encryption/decryption duties, an 128/256-bit AES accelerator block is also provided.

The EFM32 Giant Gecko from Energy Micro will begin sampling in Q1’2011 and pricing will start at $2.5 USD each in 100k quantities.  Detailed datasheets on the Giant Gecko will be released November 1st 2010.  Further information is available at www.energymicro.com

HILLSBORO, OR — JULY 19, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that it has released more than 90 reference designs optimized for the MachXO^TM and ispMACH® 4000ZE PLDs. Reference designs enable the quick and efficient design and deployment of commonly used functions such as general purpose I/O expander, I2C bus master / slave, LCD controller and SD Flash controller, as well as other interfaces, in a variety of markets including consumer, communications, computing, industrial and medical. The reference designs, coupled with complete documentation and design source code, are fully customizable and enable designers to reduce design time, boost productivity and accelerate time-to-market.

“We utilized Lattice’s I2C controller reference design using MachXO PLDs in our Ethernet Access product,” said Mr. Liang Shi Qiang, Hardware Manager at Raisecom Technology. “Lattice’s reference designs and easy-to-use development kits allowed us to design and validate a broad range of functions, enabling us to get to market quickly.”

“By delivering differentiated products that target a broad range of system and consumer applications, Lattice is gaining market share in the low density PLD market, in part as a result of making the design process more convenient by providing reference designs and easy-to-use development kits,” said Gordon Hands, Director of Marketing for Low Density and Mixed Signal Solutions. “Our comprehensive portfolio of reference designs enables engineers to rapidly prototype their products.”

Test Within Minutes and Implement Designs in Less Than an Hour

Reference designs provide a great starting point for designers to begin prototyping their designs. Each reference design consists of comprehensive documentation along with HDL source code (Verilog and/or VHDL) and test benches, many of which have been pre-implemented and validated using Lattice’s low-cost development kits.

Reference designs optimized for control applications, including I/O expansion, interface bridging, level translation and power-up sequencing using the MachXO family, have been validated using the MachXO Mini Development Kit, an easy-to-use, low-cost platform that accelerates the evaluation of MachXO PLDs. Using the preloaded mini system-on-chip (mini SoC) design provided with the development kit, designers can test within minutes I2C, SPI and UART interfaces in addition to the 8-bit LatticeMico8TM microcontroller and low power sleep mode functionality. Designers can rebuild these demonstration designs using the free downloadable reference design source codes in less than one hour. This provides a known good starting point for their own design explorations.

Alternatively, designers targeting low power applications can use reference designs optimized for the ispMACH 4000ZE family that have been fully tested and verified using the ispMACH 4000ZE Pico Development Kit, a battery-powered, low-cost platform to accelerate the evaluation of ispMACH 4000ZE CPLDs. Using the preloaded ispMACH 4000ZE Pico Power demo design provided with the development kit, designers can test I2C master and LCD controller interfaces in addition to the embedded ispMACH 4000ZE oscillator timer, then build their own designs using the free downloadable reference design source code.

Reference Design Availability

Lattice’s entire portfolio of reference designs optimized for the MachXO and ispMACH 4000ZE families can be downloaded for free from the Lattice website at http://www.latticesemi.com/products/intellectualproperty/aboutreferencedesigns.cfm

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com.

HILLSBORO, OR — JULY 19, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that it has released more than 90 reference designs optimized for the MachXO^TM and ispMACH® 4000ZE PLDs. Reference designs enable the quick and efficient design and deployment of commonly used functions such as general purpose I/O expander, I2C bus master / slave, LCD controller and SD Flash controller, as well as other interfaces, in a variety of markets including consumer, communications, computing, industrial and medical. The reference designs, coupled with complete documentation and design source code, are fully customizable and enable designers to reduce design time, boost productivity and accelerate time-to-market.

“We utilized Lattice’s I2C controller reference design using MachXO PLDs in our Ethernet Access product,” said Mr. Liang Shi Qiang, Hardware Manager at Raisecom Technology. “Lattice’s reference designs and easy-to-use development kits allowed us to design and validate a broad range of functions, enabling us to get to market quickly.”

“By delivering differentiated products that target a broad range of system and consumer applications, Lattice is gaining market share in the low density PLD market, in part as a result of making the design process more convenient by providing reference designs and easy-to-use development kits,” said Gordon Hands, Director of Marketing for Low Density and Mixed Signal Solutions. “Our comprehensive portfolio of reference designs enables engineers to rapidly prototype their products.”

Test Within Minutes and Implement Designs in Less Than an Hour

Reference designs provide a great starting point for designers to begin prototyping their designs. Each reference design consists of comprehensive documentation along with HDL source code (Verilog and/or VHDL) and test benches, many of which have been pre-implemented and validated using Lattice’s low-cost development kits.

Reference designs optimized for control applications, including I/O expansion, interface bridging, level translation and power-up sequencing using the MachXO family, have been validated using the MachXO Mini Development Kit, an easy-to-use, low-cost platform that accelerates the evaluation of MachXO PLDs. Using the preloaded mini system-on-chip (mini SoC) design provided with the development kit, designers can test within minutes I2C, SPI and UART interfaces in addition to the 8-bit LatticeMico8TM microcontroller and low power sleep mode functionality. Designers can rebuild these demonstration designs using the free downloadable reference design source codes in less than one hour. This provides a known good starting point for their own design explorations.

Alternatively, designers targeting low power applications can use reference designs optimized for the ispMACH 4000ZE family that have been fully tested and verified using the ispMACH 4000ZE Pico Development Kit, a battery-powered, low-cost platform to accelerate the evaluation of ispMACH 4000ZE CPLDs. Using the preloaded ispMACH 4000ZE Pico Power demo design provided with the development kit, designers can test I2C master and LCD controller interfaces in addition to the embedded ispMACH 4000ZE oscillator timer, then build their own designs using the free downloadable reference design source code.

Reference Design Availability

Lattice’s entire portfolio of reference designs optimized for the MachXO and ispMACH 4000ZE families can be downloaded for free from the Lattice website at http://www.latticesemi.com/products/intellectualproperty/aboutreferencedesigns.cfm

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com.