Now available from EDA Solutions is version 15 of Tanner EDA’s HiPer Silicon full-flow design suite, giving designers a complete analogue design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification.
HiPer Silicon v15 includes HiPer DevGen, the newest addition to Tanner’s portfolio that offers breakthrough device and structure generation for layout productivity. Other new features in v15 include a complete redesign of the waveform editor W-Edit, which provides designers with a signal analysis platform rather than simple layout views, and the addition of a new database for storage and management of simulation data.
“Our goal was to create a robust tool that could produce a layout of high quality while simultaneously reducing the cycle time,” said IC Mask Founder & CTO Ciaran Whyte. “Beta customers have told us unanimously that HiPer DevGen exceeds their expectations on both dimensions.”
“Tanner EDA has long been helping innovative companies create breakthrough applications in analog and mixed-signal design,” offered Massimo Sivilotti, chief scientist at Tanner Research. “Founder John Tanner always thought it was important that designers in any size company should be able to have access to software solutions that would make their jobs easier and more productive. HiPer Silicon v15 continues our commitment to that strategy.”
The new HiPer DevGen tool, developed in collaboration with IC Mask Design, is offered as an add-on option that focuses on silicon quality and yield to generate production-ready devices. By accelerating the most time-consuming aspects of the layout process, HiPer DevGen substantially reduces the amount of time required for analogue layout while improving quality and design consistency. Integrated device/structure logic ensures a consistent and high quality approach to the layout of complex analogue structures across design engineers, design teams, and engineering sites.
HiPer DevGen generates key analogue design primitives such as current mirrors and differential pairs, often the most time-consuming aspect of layout and the most critical to the functionality of silicon. It allows effortless creation of T-cells for CMOS technologies, applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield.
Tanner’s W-Edit now provides a new paradigm for post-simulation analytics, allowing designers to perform a robust set of analyses in an intuitive and cohesive user environment.
