San Jose, CA, June 30, 2010 – Atmel® Corporation (Nasdaq: ATML), a leader in microcontroller and touch solutions, today announced that it has received the “Compatible with Windows 7” logo for over 10 multi-touches on a 10.1 inch maXTouch™ technology touchscreen device. Tested in the Windows Hardware Quality Labs (WHQL), Atmel’s maXTouch technology passed the rigorous phases of this certification program. The Windows 7 logo program aims to inform consumers and help them make better purchasing decisions by identifying products via the “Compatible with Windows 7” logo that have passed Microsoft®-designed tests for compatibility and reliability on Windows 7. This program now includes the new Windows Touch qualifier.

Windows® Touch is a new feature in the Windows 7 operating system that allows users to control Windows and their application using multi-touch input. All vendors must pass this qualification step in order to achieve the Windows 7 logo. MaXTouch technology passed these steps and was qualified for more than 10 touches for this logo program.

To assist partners with preparing for the Windows Touch tests, Microsoft established the Windows Touch Test Lab (WTTL), also commonly known as the Windows Hardware Quality Labs (WHQL) testing. This Microsoft facility helps partners validate the quality of their multi-touch digitizers for use with Windows Touch. The facility also provides the test services necessary to qualify multi-touch devices, such as the Atmel maXTouch solution, for the Windows 7 logo program.

“As a leader in the touch technology space, Atmel is committed to offering consumers the highest reliability and functionality for their touch applications,” said Binay Bajaj, sr. manager of touch marketing, Atmel Corporation. “By offering more than 10 touches, Atmel provides designers a robust platform to develop new and exciting touch applications. Furthermore, this functionality allows the rejection of unintended touches including face detection on mobile phones, grip suppression, and palm rejection on mobile Internet devices and netbook screens.”

“Microsoft is pleased that Atmel has earned the Compatible with Windows 7 logo for the maXTouch technology,” said Mark Relph, senior director for Windows Product Management at Microsoft Corp. “This highlights Atmel’s commitment to providing its customers with products that are more intuitive and interactive, and compatible with Windows 7.”

Atmel maXTouch solutions offer superior performance and low power consumption. The maXTouch devices support an unlimited number of touches and stylus, greatly enhancing the user experience and changing the way users interact with electronic products. These solutions are optimized for small and large touchscreens up to 15″. For more information on maXTouch solutions, visit:http://www.atmel.com/products/touchscreens/default.asp?family_id=701.

More Information and Video

For additional information on Atmel maXTouch for large screens products and to view our latest touch video, please visit:http://www.atmel.com/maXTouch_goesbig.

About Atmel

Atmel Corporation (Nasdaq: ATML) is a worldwide leader in the design and manufacture of microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry’s broadest intellectual property (IP) technology portfolios, Atmel is able to provide the electronics industry with complete system solutions focused on industrial, consumer, communications, computing and automotive markets.

San Jose, Calif. (June 30, 2010) – GSA, the voice of the global semiconductor industry, recently hosted a  panel of European analogue IC design experts at the GSA & IET International Semiconductor Forum in London on 19 May.  The discussion led to a possible solution to the analogue IC design bottleneck. The Global Semiconductor Alliance together with the UK’s Institution of Engineering & Technology joined forces to highlight and discuss European trends in semiconductor development. This year’s program focused on leveraging and maximising European expertise in analogue/mixed-signal, wireless, low-power applications and quality/reliability to access emerging markets for silicon growth including smart cards, power electronics and home networking.

“The panel addressed the problems facing today’s analogue designers, including technology and design issues, which are the cause of the analogue bottleneck,” explains panel chair Paul Double, GSA’s European chair of the Analogue/Mixed-Signal Interest Group and founder and managing director of EDA Solutions Limited. “The discussion resulted in a proposed new methodology for IC design which leads to faster layout, allowing early analysis of the extracted design,” added Double.

Market research indicates that although analogue circuitry comprises only 20% of the area in today’s modern mixed-signal devices, it is likely to account for some 80% of yield loss. Due to the complexity of the design and dramatic increase in process related design rules to be considered, mixed-signal design, and especially full custom design, is leading to more errors and performance related problems.  Manual design and layout is no longer viable, yet automation in the analogue design world remains difficult, and is often an anathema to analogue designers. This quandary is often referred to as the analogue bottleneck.

The findings of the panel discussion suggested a new approach to analogue design to help offset this bottleneck. Because analogue layout at the deeper process nodes is heavily dependent on processing effects, it often does not make sense to perform simulation before the layout stage as in a traditional IC design flow. The solution proposed by the panel to achieve faster layout is to allow early analysis of the extracted design. The flow from schematic to layout has to be accelerated, with simulation only after parasitic extraction. This requires a change in CAD methodology to accelerate the manual layout process.

The existing approach is currently: circuit entry in schematic form, simulation, adjust the schematic, re-simulate, repeat until satisfied with simulation and then on to layout and finally, verification of layout. The new approach proposed by the panel is: schematic, directly to layout, verification including extraction of layout complete with parasitics, simulation, then repeat the entire process until simulations are satisfactory. To support this new methodology, IC design software must feature robust device layout generators, correct by construction placement tools and an integrated router, to enable early analysis and characterization.

Present on the GSA & IET analogue panel were Ross Addinall, Europe technical director at Ciranova, Peter Frith, chief technical officer of Wolfson Microelectronics, Doug Pattullo, director of Field Technical Support at TSMC Europe and Ciaran Whyte, co-founder and chief technical officer at IC Mask Design. The panel was chaired and moderated by Paul Double, GSA’s European chair of the Analogue/Mixed-Signal Interest Group and founder and managing director of EDA Solutions Limited.

About GSA:

The Global Semiconductor Alliance (GSA) mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective fabless ecosystem through collaboration, integration and innovation.  It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions.  Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence.  Members include companies throughout the supply chain representing 25 countries across the globe. www.gsaglobal.org