COMPUTEX TAIPEI, Taiwan – June 1, 2010 – MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, today announced that ViXS Systems Inc. will demonstrate the Android™ platform running on its MIPS-Based™XCode® 4200 family of Integrated Chipsets at COMPUTEX TAIPEI this week. The XCode® 4200 family is a fully-integrated dual HD transcoder SoC family designed specifically for Blu-ray, NAS (network-attached storage), IPTV/cable/satellite set-top boxes, home gateways and other consumer entertainment devices.

A global leader in innovative and advanced networked multimedia solutions, ViXS separately today introduced an Android software development kit (SDK) for the flagship IC XCode® 4210. ViXS joins a growing list of innovative companies leveraging Android on the MIPS® architecture to create the next generation of connected entertainment devices.

“Next generation connected entertainment platforms will require a full web experience and a rich graphical user interface with high-performance processing, full HD, 3D graphics and other advanced functionality,” said Art Swift, vice president of marketing, MIPS Technologies. “With the increasing number of formats and standards, real-time transcoding technology is clearly a must for Blu-ray players, set-top boxes, home gateways, and other advanced digital home products, and this is the first time we are seeing it available for Android. With the high-performance, feature-rich XCode® 4210, ViXS is really taking advantage of the power of the MIPS architecture.”

“The functionality and processing power of the XCode® 4210 in combination with the MIPS architecture provides a feature rich platform for Android. This platform allows our customers to access the suite of applications available with Android and to provide a truly connected experience to the consumer,” said Sally Daub, president and CEO, ViXS Systems.

Specifically designed for 3D TV applications, the XCode® 4210 includes full 3D TV display formatting capability, 2D/3D graphics rendering, and the latest H.264 Multi-view Codec (MVC) 3D TV decoding standard. The XCode® 4210 delivers user performance in excess of 3,200 DMIPS distributed over a main MIPS MIPS32® 74Kf™ applications processor and two offload processors, all simultaneously running their own real time operating systems.

The XCode® 4210 simultaneously encodes, decodes and transcodes HD video up to 1080p60/50. It has the ability to transcrypt and transcode many forms of multimedia content to many multimedia and container formats. This enables seamless streaming, downloading and sideloading to a wide range of connected consumer entertainment devices, such as set-top boxes, PC/laptops, DTVs, game consoles, Blu-ray players, DLNA clients, wireless tablets and smart phones. With ViXS’ real-time transcryption, protected content remains secure between devices, and its real-time transcoding provides streaming efficiency to save bandwidth and increase storage capacity.

About Android on MIPS

Leveraging its leadership position in the digital home, MIPS Technologies is spearheading efforts to make Android a reality for a wide range of consumer electronic devices. With Android and the dynamic open source development community around it, developers can easily and quickly create new applications, and OEMs can leverage a fast-growing set of applications for their devices. The extensive MIPS ecosystem around Android enables OEMs to quickly optimize Android for their specific platforms and debug their solutions across the entire software stack. For more information about the Android platform and MIPS Technologies, or to access the full source code for MIPS Technologies’ port of Android to the MIPS32® architecture, including a reference binary, tools and documentation, please visitwww.mips.com/android or email android@mips.com.

About MIPS Technologies, Inc. (www.mips.com):

MIPS Technologies, Inc. (NasdaqGS: MIPS) is a leading provider of industry-standard processor architectures and cores that power some of the world’s most popular products for the home entertainment, communications, networking and portable multimedia markets. These include broadband devices from Linksys, DTVs and digital consumer devices from Sony, DVD recordable devices from Pioneer, digital set-top boxes from Motorola, network routers from Cisco, 32-bit microcontrollers from Microchip Technology and laser printers from Hewlett-Packard. Founded in 1998, MIPS Technologies is headquartered in Sunnyvale, California, with offices worldwide.

MOUNTAIN VIEW, Calif. – June 2, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, today announced new versions of ActiveDesign™ and JasperGold® with capabilities that bridge the divide between chip design and verification by sharing a common, persistent knowledge base.

Jasper’s ActiveDesign with Behavioral Indexing™ lets users design, concurrently modify, and verify their RTL code, then store it in a persistent database containing both the RTL itself and an “index” of its elastic behaviors.  This information is shared downstream with the JasperGold verification team, facilitating increased collaboration between groups.  Benefits are unity among multiple design groups and verification teams, a reduction in information demand on designers, acceleration of verification, and increased IP reuse since design behaviors are now archived and easily accessible.

“ActiveDesign with Behavioral Indexing is the core technology that allows RTL developers to store information, building persistent value databases that can later be used by other designers or verification engineers,” said Dr. Rajeev Ranjan, Jasper Chief Technology Officer. “ActiveDesign and JasperGold work synergistically.  Designers using ActiveDesign explore blocks, waveforms and their key behaviors, creating and archiving important information.  ActiveDesign can then export properties (asserts, assumes, covers, in SVA and PSL) for transfer to other designers or verification teams using JasperGold.” In addition to the new unified design-to-verification flow, Jasper has added several new capabilities to its tools to increase rapid adoption, high-level verification acceleration, and increased ROI for formal verification users.

ActiveDesign Version 2.0

Version 2.0 of ActiveDesign, named an EDN Hot 100 Product in January, includes the ability to share information with JasperGold as described above, along with several new, automated fast-start and collaboration features.

EasyStart automates the identification of clocks and resets so designers can explore new RTL blocks faster.  AutoExplore examines behaviors of interest by displaying contributing causes and paths back through the design to show causality.  With concurrent modification, different designers can work on the same code while an intelligent management system prevents overwriting.  ActiveDesign’s hierarchical design support lets an RTL block be instantiated repeatedly at different levels in the design to efficiently deal with complexity, and a new parallelization feature distributes ActiveDesign across multiple platforms for increased throughput.

JasperGold/JasperCore™ Version 7.0

The JasperGold Formal Verification System now has 50% higher performance and capacity, aided by new engine technology and modeling abstractions. ProofGrid and new ProofGrid Manager support user-controlled and distributed proof engines to reduce the time needed to reach full proofs. A new management capability accelerates convergence of deep formal proofs, leveraging Jasper’s leading design-space tunneling and promoting both proactive and after-the-fact RTL tree exploration of design complexity.  And versatile JasperGold now has enhanced handling of the toughest formal verification tasks such as X-propagation, multi-cycle path analysis, clock domain crossing (CDC), and certification of the latest protocols such as DFI and AMBA 4 (enabled by designer-friendly Jasper Proof Kits). 

About Jasper Design Automation

Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments.  Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.