Simple. One number. 180.
The maximum current draw of a bipolar technology PAL16L8A in a 20-pin CERDIP or plastic SKINNY-DIP package across the commercial operating range.
You wanna know how much current must be sourced? Easy. 180 mA. Period.
Ah… those were the days. We were so innocent back then. Somewhere along the way some marketing guy noticed that, especially with the new-fangled CMOS technology, PLD power consumption varied with the pattern in the device. And that was the start of the slippery slope.
We went from “here’s the guaranteed number” all the way to “we don’t know, we don’t guarantee anything, and, now that you’ve yelled for long enough, we sort of have a kind of tool that will let you estimate your current for your design, but we still don’t guarantee anything and you’re on your own so don’t come running to us if your system explodes.”
And FPGA vendors were completely off the hook. How much does my chip draw? “It depends.” Nice.
Most chip designers aren’t so lucky, but, even so, with complex ICs entertaining a multitude of possible scenarios (“modes” or “use cases” in marketing parlance), it still gets really hard to put your finger on exactly how much power a chip should draw.
Which gets to the question, just what determines how much current should be allowed? Of course, in this era, battery life trumps all. Being able to paint your logo green is also useful (and, on top of that, saving energy is a bonus). But there are other more venerable and less fashionable reasons that set a limit on power, and these date back to the days of bipolar and before.
Things like, you don’t want to melt the plastic package.
Things like, if you exceed the operating conditions for which the chip was designed, well, your mileage may vary.
Things like, you don’t want to accelerate the wear-out of the chip early and cause reliability problems.
So how do we figure all this out? Well, this takes us to the other side of the tracks, where the world is just a bit grimier and, well, real. The world of the mechanical engineer. And yet, in many ways, it’s not as different from our own as might be thought.
The basics that lead to your power budget used to be pretty accessible to any designer or product engineer, but, given the scale of projects and the level of specialization, it’s likely that many engineers never have to peer into the realm of the thermo-mechanical.
So here are some basics. Your chip generates heat. That heat travels through a package to the outside world. It might just go through plastic or it might have the help of thermal spreaders or other internal gadgets intended to supplement the conductivity of plastic. Or you might have a more conductive material than plastic.
Once at the edge of the package, that heat has to go somewhere or it will stop flowing. It might just drift off the package into the ambient, or you might need something more aggressive like a heat sink to pull the heat out of the package faster or perhaps moving air or even liquid to get the heat away from the package as fast as you can.
The questions are, how much of this stuff do you need and how much heat are you allowed to generate in your chip? Obviously the more elaborate the cooling gadgetry, the more expensive your chip is.
And here’s where the worlds merge a bit: the thermal characteristics are modeled as circuits. There’s an analogy between electrical current and heat flow; between voltage and temperature (or, more accurately, temperature differential); and between resistance and, well, what’s called thermal resistance. It’s not too difficult to visualize the meaning of thermal resistance; plastic would have higher resistance than metal, for example.
Packages are characterized with respect to various thermal resistances from one point to another. The greek letter theta is used for the resistance, so, for example, the resistance between the silicon junction (J) and the package case (C) is ΘJC. In the olden days, all the characterization was done with probes and thermocouples placed just so for measuring heat dissipation. And the number of configurations to be considered wasn’t particularly daunting when you could pretty much count on a few simple configurations like having power on the corner pins, with inputs on the left and outputs on the right.
Not so easy with the kilo-bump behemoths that now swaddle our giga-gate babies. And the number of package component configurations and combinations has jumped as well. And, if that weren’t enough, there may be pinout sensitivities – especially when you start relying on your pins to wick heat away from the chip.
Here again, our worlds start to look alike: the thermal folks now simulate the packages using sophisticated modeling tools. Of course, while it’s much easier than actually doing physical measurements, it’s still a time-consuming process meticulously creating and assembling all the necessary models for doing a thorough package simulation. Just like it is with circuit simulation.
So you can imagine that it can get tedious in the characterization simulation lab with everyone and their uncle calling in and asking for the thermal characteristics of various flavors and variants of packaging.
The thing is, there are characterization requests, and then there are special characterization requests. JEDEC provides an assortment of “approved” packages. Once upon a time that was enough to be able to do the measurements and simply publish numbers. But even amongst standard packages, there are many ways to assemble and combine the constituent pieces, so no one has measured all possible configurations. Many of the requests are simply for a different arrangement of JEDEC standard components.
Mentor has approached this as an opportunity. Through their purchase of Flomerics, they acquired a tool called FloTHERM which is a full thermal simulator with which any package (or other physical entity) can be characterized. But in order to simplify those characterization requests that involve different permutations of JEDEC-approved bits and pieces, they have spun off a separate tool called FloTHERM-IC. They’ve built a database of existing results; this, combined with their solver, allows calculation of the JEDEC metrics and models, as well as sensitivity analysis, of any combination of the JEDEC-approved package elements they support.
Instead of having to painstakingly craft and simulate a package model, you get a wizard that guides you through the process of configuring the package using a library of supported components. You can then request information about that package without going through full simulation.
One unusual aspect of the tool is that it is web-based: the business is operated on a software-as-a-service (SaaS) basis, although it’s a tad short of cloud computing in the sense that most now use the phrase. The service is hosted on two Mentor servers that get pulled into duty for each request. One server holds the database; the other runs the solver. So it’s a two-server private cloud. Users subscribe on a yearly basis.
So now those more routine requests can be handled quickly, saving the grueling simulations for those special custom package requests or when you’re trying to do something you don’t want JEDEC to know about.
And all of this effort is for you. So you can get your power budget. That budget that you probably won’t guarantee to your customer any more.
All this work so that a marketing weasel can say, “It depends.”
Why, back in my day, we guaranteed a number. And the number was 180…
More information: FloTHERM-IC