Irvine, California, April 12, 2010 – Advantech, a global manufacturer of telecom computing blades and multi-core network platforms, announced today that it has shipped its first batch of FWA-6500 dual processor appliances. The FWA-6500 is based on the Intel® Xeon® Processor 5600 Series. 

The FWA-6500 features dual processor computing performance for high-speed modular I/O processing of multiple GbE and 10GbE links. Purposefully built for high-end network security and packet processing applications, the system takes advantage of the Intel® AES New Instructions (Intel® AES-NI) which frees up valuable processor cycles for more virtualization and processing. Intel® AES-NI adds new instructions which provide robust encryption without the need for additional appliances or increased performance overhead. 

Additionally, Intel® Trusted Execution Technology (Intel® TXT) performs SHA-1 hash measurements for RSA decryption key exchanges as part of the code authentication process. This means greater security in network transactions without a loss in processing power.

The Intel® Xeon® processor 5600 series is manufactured around Intel’s latest 32nm process technology and is pin-compatible with the Intel® Xeon® processor 5500 series, allowing OEMs to add higher performance platforms to their offerings or to migrate their production to the new 6-core processors. The drop-in compatible 6-core processors allow a smooth upgrade path to the deployed base with minimal to no impact on software applications.

The new processor series brings significant improvements in core density, performance and power consumption as well as new instructions to accelerate encryption and reinforce security.  With up to 6-core operation (up to 12 threads per socket with Intel® Hyper Threading Technology), 50% L3 cache increase to 12 MB, and support for lower voltage DDR3L DIMMs, the capabilities of the new processors will facilitate further platform consolidation whilst decreasing power budget. 

Network connectivity is fast and flexible with up to 16 front accessible GbE ports supported by 4 quad Gigabit Ethernet modules, based on the Intel® 82576EB Gigabit Ethernet Controller, or, multiple dual 10GbE modules based on Intel’s 82599EB 10 Gigabit Ethernet Controller. The modules plug into a 32-way PCI Express (PCIe) gen2 mid-plane, providing high speed interconnects to the I/O controller hub, making the system fast and efficient. RJ45 and SFP/SFP+ based modules are supported and can be mixed and matched as required. Copper modules come with optional LAN bypass capabilities.

“Networking customers are looking for off-the-shelf platforms where processor cores get fed with maximum I/O subsystem bandwidth, therefore benefiting from modular and innovative I/O connectivity with controlled thermal performance,” said Eddie Lai, director of business development for Advantech’s network and telecom group. “The FWA-6500 gives them just that. Once they have successfully benchmarked and tuned the software, Advantech begins the system branding or customization process with OEM packaging and global logistics support. We are there to accelerate and facilitate global deployment.”

Two further PCIe x4 slots are available internally for standard add-in cards for offload purposes or network processor–based co-processing. The combination of the latest Intel® processors, chipset and Ethernet controllers in one platform provides acceleration and off-loading features giving customers the ultimate in x86 processing performance, and accessibility to all the I/O scalability they need.

“The Intel® AES New Instructions, in the Intel® Xeon® processor 5600 series, are designed to accelerate tasks such as whole disk encryption/decryption, internet security and VoIP,” said Frank Schapfel, product line marketing manager at Intel’s performance products division. “Accelerated hardware cryptography in processors is becoming more mainstream across multiple applications and market segments.”

“The modular IO concept is the backbone of our high end and mid-to-high end network application and server platforms to be consistently supported on our next generation designs,” said Rover Chen, director of x86 appliance products for Advantech’s networks and telecom group. “This approach gives customers the opportunity to upgrade to next generation motherboards or next generation IOs without the hassle of designing and qualifying a completely new system. This also applies to ODM customers with unique IO and system requirements – once a customized IO board and enclosure design is done, customers can enjoy free technology upgrades on the motherboard driven by Advantech’s standard roadmap. Our membership in the Intel® Embedded Alliance enables us to deliver our latest platform technologies coincident with Intel’s product releases.”

For more information about the FWA-6500, visit Advantech networks and telecom at www.advantech.com/NC, E-mail NCG@advantech.com or call toll free: 1-800-866-6008

Pricing

FWA-6500BE

2U Xeon (Up to 2.53ghz) appliance w/ LCD, 1x COM, 2x USB, 2x mgmt LAN (10/100), no Express Module LAN cards included, 2x PCI-E x4 slots w/x16 connector, 2x 2.5″ SATA H/S bays, 600w 1+1 AC ATX RPS
NEW  $4,200

FWA-6500CRE

2U Xeon (Up to 2.53ghz) appliance w/ LCD, 1x COM, 2x USB, 2x mgmt LAN (10/100), includes 4x NAEM-0103E LAN cards (16x 10/100/1000 ports w/ LAN bypass), 2x PCI-E x4 slots w/x16 connector, 2x 2.5″ SATA H/S bays, 600w 1+1 AC ATX RPS
NEW  $5,70

MOUNTAIN VIEW, Calif., April 12 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the Best Paper Awards for the twentieth annual Synopsys Users’ Group (SNUG®) San Jose conference, held in Santa Clara, Calif. on March 29-31. First place was awarded to Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee and Bruce Doyle of AMD and Zhi-Yuan Wu of GLOBALFOUNDRIES for “Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design”; Alvin Loke won the Best First-time Presenter Award for presenting this paper. Second place was awarded to Gerard M. Blair of LSI Corporation for “Hold is not setup (derate is not OCV).” Third place was awarded to Paul Zimmer of Zimmer Design Systems for “‘There’s a better way to do it!’ – Simple DC/PT Tricks That Can Change Your Life.”

The SNUG Technical Committee Award went to Avishek Panigrahi and Arvind Parihar of MIPS Technologies, Inc. for “Clock Power Reduction-Analysis Metrics and Power Reduction Techniques.” The Technical Committee Honorable Mention Awards went to Krishna Vittala of Microchip Technology Inc. for “Reusable UPF for Multi-Voltage Designs & Handling Analog Macros in Power Subsystems,” and to Asif Jafri with Verilab Inc. for “Interoperable Testbenches using VMM TLM.”

SNUG San Jose is part of the largest user conference program in electronic design automation (EDA). In 2009, the program attracted more than 7,000 integrated circuit (IC) and system design engineers to open forums in the U.S., India, Taiwan, Singapore, Europe, Israel, China and Japan. Attendees represent the world’s largest semiconductor design and manufacturing companies as well as many innovative start-ups.

More than 2,000 technical users attended this year’s San Jose event, which marked twenty years of close, continued collaboration between Synopsys and its users. The milestone event included a number of highlights, including the participation of industry luminaries Doug Grose (GLOBALFOUNDRIES), Rick Cassidy (TSMC) and Moshe Gavrielov (Xilinx) who shared their latest perspectives on the evolving industry. For the first time this year, technology tracks for system-level design and compute infrastructure were offered, allowing users access to an expanded program of technology tracks. SNUG San Jose 2010 also marked the first Designer Community Expo, which showcased the integration between Synopsys and more than 50 of its partners from across the electronics industry who provide solutions that address the difficult design challenges SNUG attendees face.

“SNUG was established with a mission to create a rich channel of communication for users to interact with each other and with Synopsys. Twenty years later, that mission hasn’t changed,” said John Busco, Design Implementation manager, NVIDIA, and SNUG San Jose Technical Chair. “Countless papers, presentations and reunions through the years have brought shared learning and enrichment to thousands of engineers seeking an environment full of technical facts and ideas to help them better address the growing challenges of electronic design, verification and manufacturing. As a user, I look forward to many more years of shared experience through SNUG conferences.”

Aart de Geus, chairman and chief executive officer at Synopsys, opened the conference with a keynote sharing his perspective on some important trends. de Geus highlighted SNUG San Jose’s 20th anniversary as a testament to EDA’s growth and endurance as a highly collaborative, forward-thinking industry. He also spoke about a number of Synopsys’ exciting technology developments including Design Compiler® 2010, which is the latest RTL synthesis innovation within the Galaxy(TM) Implementation platform, as well as the company’s expanded activities in the system-level design space with the recent VaST and CoWare acquisitions.

“SNUG’s continued evolution has been integral to its longevity as a forum for designers to collaborate with Synopsys and each other,” said de Geus. “I am grateful for these opportunities to meet with and learn from our users. I’m always impressed by the wonderful ideas shared at SNUG and the quality of papers submitted. This shared vision helps Synopsys continuously expand our portfolio to address the latest design challenges.”

SNUG San Jose 2010 sponsors include: Platinum Sponsors ARM, GLOBALFOUNDRIES, IBM, Samsung Electronics Co., Ltd. and TSMC; Gold Sponsors Altera Corporation, HP, Virage Logic, Xilinx and Zuken; and Silver Sponsors Agilent Technologies and Doulos. The three-day SNUG San Jose conference featured a technical program with 85 presentations, including 36 user papers and 43 Synopsys technical sessions. The presentations focused on challenges that engineers face today in all areas of design, including synthesis, verification, low power design, physical design/sign off, analog/mixed-signal design, custom design, test, IP, embedded software development, rapid prototyping tools and compute infrastructure.

Please visit the Synopsys Users Group website at http://www.snug-universal.org/ for more information on upcoming events and how to submit a paper for consideration by the SNUG technical committee. Customers can also access proceedings and the award-winning papers at this link.

About Synopsys

Synopsys, Inc. (NASDAQ:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

HILLSBORO, OR — APRIL 12, 2010 — Lattice Semiconductor (NASDAQ: LSCC) today announced the availability of a new low cost PCI Express development kit for its award winning LatticeECP3™ family of high value, low power FPGAs.  Based on a new ECP3 PCI Express solutions board, the kit accelerates development of PCI Express designs.  The kit has been developed from the ground up to accelerate the evaluation of Lattice PCI Express technology, demonstrate a range of solutions that match typical application requirements and speed users to design exploration.  Lattice will demonstrate the LatticeECP3 PCI Express development kit at the 13th Embedded Systems Expo (“ESEC”), Booth 37-26, in Tokyo, Japan from May 12th to May 14th.

The new kit features four key capabilities for quick evaluation and rapid prototyping of low cost PCI Express system design.  First, the kit enables users to bring up running PCI Express hardware in thirty minutes or less.  Second, various demos included in the kit address control plane through data plane performance requirements.  Third, source files for the demos are available that enable rebuilding designs up to a known good starting point.  Finally, the kit enables a rapid transition to design exploration through the included software tools, IP enabled evaluation process and project source directories.

“The LatticeECP3 FPGA is an excellent low power, high value programmable platform for PCI Express,” said Shakeel Peera, Lattice’s Director of Strategic Marketing for High Density Solutions.  “The new LatticeECP3 PCI Express development kit will help users reduce complexity and shrink the time-to-market window for their PCI Express designs.”

About the LatticeECP3 PCI Express Development Kit

The LatticeECP3 PCI Express development kit offers several key features for rapid, low-cost PCI Express system design:

• An all-inclusive package that is optimized for creating a design with the low-power, low-cost LatticeECP3 FPGA family.
• A highly-optimized, low-cost PCI Express evaluation board that enables both x1 and x4 endpoint evaluation and design.
• A variety of demo executables – basic demo for control plane applications, throughput demo for high-bandwidth applications, color bar demo and an image transfer demo – that show how to address different design performance requirements.  
• A 60 day software tools license and included x1/x4 endpoint IP core and scatter-gather DMA IP core permit users to get up and running right away.
• Available on both Windows and Linux platforms.

The components of the LatticeECP3 PCI Express development kit have been configured to work together to enable fast system evaluation and design.  With the help of easy step-by-step instructions, designers can expect to have a demo running in as little as 30 minutes, and a design validated in less than two hours.  For more information visit: http://www.latticesemi.com/products/developmenthardware/developmentkits/pciexpressdevkitec

About the LatticeECP3 FPGA Family

The award winning LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing.  Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits.  Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.  The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireline and wireless infrastructure applications, as well as security/surveillance, medical and industrial applications.

Pricing and Availability

The development kit is available now, with a list price of $895.00.  The kit can be ordered through Lattice sales or through the Lattice on-line store at http://www.latticesemi.com/store/dev_kits.cfm.

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions.  For more information, visit www.latticesemi.com