Almost every design built within an FPGA requires the use of internal memory resources of some size for storage of coefficients, buffering of data, and a variety of other uses. Typical systems need a combination of small, medium, and large memory arrays to meet all of their requirements, with the overall power consumption of the memories, and therefore the FPGA, being a primary concern.

When laying out an FPGA, it is important to create a device that meets the majority of customer needs. If an FPGA is built with small, medium, and large memory resources that perfectly suit one application, the solution will be optimal for some customers while others wanting to use the same part will likely need to make considerable trade-offs.

Users trying to get the best value out of their FPGAs can be concerned about wasted bits in larger RAMs. Building finer RAM granularity, though, requires additional FPGA interconnect, at a cost. This white paper explains the trade-offs: why the cost of finer RAM granularity is often higher than the cost of otherwise wasted bits.

Author: Nick Mehta, Senior Applications Engineer, Xilinx