Don’t try to understand how Tabula’s 3D FPGA fabric works. You don’t need to know that. All you have to do is wait until they announce a family based on the new technology, and then you can buy bigger, faster FPGAs for less money. And, yes, you can keep using your standard HDL-based FPGA design methodology.
You can stop reading now.
Why are you still here? Do you think we’re going to explain what “spacetime” means, and how an FPGA could possibly be 3D? Are you expecting to hear about logic cells being resource-shared and time-multiplexed at super-high frequencies, creating a virtual logic fabric with up to eight times the density of the physical silicon?
All you need to do is wait a little while, start your next project, check out Tabula’s datasheet, and tell your boss “Hey, these are really big FPGAs. I don’t know how they make them this size for so cheap, but we could use some of that extra capacity right about now.”
OK, you’re determined to keep reading, aren’t you. You’ll be sorry. You won’t have that nice, plausible deniability where you can safely claim not to understand. At some point, you’ll find yourself drawing crazy diagrams on the whiteboard while your boss squints his eyes and drums his fingers on the table…
Tabula has been in “stealth mode” perhaps longer than any company in the history of the concept of “stealth mode.” For years now, every spring we wait and watch expectantly while Tabula peeks out of their burrow, sees their shadow, and goes back underground for another year of venture-funded silence. In fact, Tabula was founded in 2003, has over 100 employees, and has secured a hefty $106M in venture funding to date. Why so long and so expensive? Because starting a new FPGA company is difficult. As we’ve seen proven again and again, time, talent, and money are all three required – and with mask and NRE costs escalating exponentially, the challenge gets harder every year.
Tabula is now breaking their silence and preparing to come to market with a radical new architecture they call “Spacetime.” Tabula describes Spacetime as a 3D FPGA architecture. By doing some very clever work in the architecture and tools, the company claims some impressive improvements in effective density of their FPGAs.
Close your eyes and picture a LUT – the basic logic cell for all of FPGAdom. Now, imagine that your LUT can connect to surrounding LUTs by programmable interconnect. Got it? You are now picturing a normal FPGA. Now, imagine that there are LUTs also located vertically above and below your LUT. (There aren’t, but keep pretending.) Now, imagine that your LUT also includes some hardware that allows its inputs and outputs to be stored, and its truth tables to be re-programmed very quickly. Let’s put a very fast clock and controller on that hardware so that your LUT is being constantly reprogrammed and cycled through eight different implementations. We’ve just created a LUT that is 8-way resource shared.
Tabula does exactly this with Spacetime. A 1.6 GHz clock toggles every LUT on the device to cycle through 8 different programs, creating a virtual 3D fabric. Any given LUT can connect to other logic on the same level with conventional interconnect, or to logic on other levels through a “time via” (a set of registers that hold the inputs and outputs until a subsequent reconfiguration). The Spacetime clock and the reconfiguration are transparent to the user. The user clock will be running at a much slower rate – typically something like 200MHz (allowing all 8 folds of the spacetime clock to complete in one user clock cycle).
Every physical LUT on the device now counts as 8 possible LUTs, giving us a theoretical 8-fold density increase. Sounds like a good trick, but how do we design for it? That’s the best news of all. The complexity of the architecture is absorbed by the placement and routing tools. Place-and-route views the device as a 3D array of logic cells. Your HDL design is identical to what you’d use on a normal FPGA. Your synthesis and simulation tools don’t know the difference (OK, that’s a bit of a lie on synthesis – we’ll explain in a bit). The place and route tools take the resulting netlist and map it to a 3D configuration of logic elements, managing the regular programmable interconnect and the time vias in the background.
There are some very nice side-benefits of this approach. First, let’s think about routing proximity. Since LUTs are now arranged in a 3D space, the distance from any given LUT to the next LUT in the netlist is now much shorter, or the number of LUTs that are close by is much larger. Shorter interconnect means easier timing closure. In fact, the interconnect that goes through time vias has a very predictable timing profile because it is simply latching values through a known number of Spacetime clock cycles. Also, the smaller size of the die relative to the number of “virtual” LUTs means the device requires less overall routing resources. In most FPGAs, routing resources are the dominant consumer of area. The knock-on effect of the physical LUT fabric being smaller is that the physical routing resources are proportionally smaller as well.
Tabula does the same trick with RAM, which has the windfall bonus of every RAM being effectively 8-port memory. Compounding the advantage – conventional FPGAs use 2-port RAM (with the corresponding 2X area penalty), but Tabula’s architecture uses single-port memories to achieve the 8-port effect, so the result is 4x the ports of conventional FPGA memory with double the density.
There is always a price to be paid for a novel architecture. Since just about every FPGA or programmable logic startup has some kind of radical new architecture, the key is always mitigating the negatives. The most common mistake made by FPGA startups is allowing their architectural innovations to impact the development process. Tabula appears to have avoided this mistake. Their architecture works with conventional FPGA design techniques. The only difference is that the company plans to require us to use their proprietary synthesis as well as place-and-route. If they did the job right, however, there are considerable benefits to be had from combining synthesis with place-and-route, particularly in these days of interconnect-dominated delay.
So, what is the Achilles’ heel of Tabula’s Spacetime? We’d suspect it would be power consumption. Having the entire chip toggling away at a brisk 1.6 GHz all the time sounds like a lot of dynamic power consumption to us. The company claims it has mitigated the power consumption problem, however, so we’ll have to wait for their actual device announcements, datasheets, and dev kits to find out what that means.
Another typical hurdle for FPGA startups is field support. The established FPGA companies rely heavily on their trained and seasoned worldwide AE teams. Tabula’s management team is made up of industry veterans, so they probably haven’t forgotten that part.
Overall, the new architecture is exciting and promising. Tabula says they’ll follow with an announcement of actual product in the near future, so we’ll be waiting to report on that. Tabula is attacking the communications infrastructure market – which is the cash cow of the entrenched FPGA superpowers, so we can expect a good fight.