BEDFORD, MA – February 23, 2010 – GateRocket, Inc., the leading supplier of verification and debug solutions for advanced FPGAs, today announced the availability of the newest version of its RocketVision® debugging software, further enhancing the company’s innovative approach to reducing design time for high-end programmable devices from Altera and Xilinx.

RocketVision 5.0 introduces new capabilities that allow designers to select individual design blocks to run in their simulator or GateRocket’s RocketDrive® hardware verification system, the industry’s only Device Native® approach to debug and verification. The features enable engineers to find and fix bugs faster, and avoid unnecessary re-runs of time-consuming synthesis-to-place-and-route iterations, reducing overall design bring-up time by 50% or more compared to traditional approaches.

The new enhancements improve the overall efficiency of RocketVision, a software-based debugging tool that is used in conjunction with popular simulation tools and GateRocket’s RocketDrive hardware verification product. It provides simulators with visibility into the FPGA hardware and enables automated diagnosis by comparing intended behavior with actual results in the FPGA.  With the new software release, designers now have the ability to move instances of one or more design blocks that were executing in the FPGA to run in the simulator. 

The user can then make changes to the RTL to fix bugs in their design and simulate them in software while the rest of the design executes in the native FPGA hardware in the RocketDrive. 

“The significant increase in complexity and size of leading-edge FPGAs has put a strain on traditional verification and debug methods. GateRocket is focused exclusively on this FPGA debug crisis, providing a unique way to locate design errors, quickly correct them, and re-verify the entire design,” said Dave Orecchio, GateRocket CEO.  “These new enhancements streamline that process even more, allowing designers to fix problems on individual portions of their design without having to go through the entire design cycle each time. This approach has a dramatic impact on debugging efficiency for complex designs.”

New features streamline debug process

The new SoftPatch feature allows engineers to try a “soft” RTL fix to the FPGA without rerunning synthesis and place-and-route, eliminating hours of unproductive waiting time.  Typically, when a bug is discovered, each correction requires a new synthesis and place-and-route cycle, and it can take days to resolve each bug.  This is especially problematic in complex FPGA designs which commonly have large amounts of unfamiliar IP and hundreds of thousands of design elements. The SoftPatch feature provides an intuitive and efficient way to sequence through each bug and test fixes for them without re-building the FPGA.  In this way the user can verify multiple fixes in a single day and then perform an overnight build that encompasses all the changes – saving weeks or months over the course of a project.

The new version of RocketVision also includes an enhanced AutoCompare features that helps identify bugs at the block or full-chip level. It allows designers to automatically compare the signals between the RTL and hardware representations of the complete FPGA design and highlights any differences that occur. This significantly simplifies the debugging process and helps quickly identify the location of each divergence.

Pricing and Availability

Both the latest versions of RocketDrive and RocketVision now support 64-bit versions of the industry’s most popular simulators from Mentor, Cadence and Synopsys.  This enables the use of the RocketDrive with 64-bit simulation servers, which are increasingly necessary to handle the largest complexity FPGA designs.

RocketVision 5.0 is a RocketDrive option and is available immediately with a starting price of $9,500.

About GateRocket

GateRocket, Inc., located in Bedford, Mass., offers electronic engineers the first Device Native® verification and debug solution for advanced FPGA semiconductor devices. The company’s RocketVision® software debug tool and its RocketDrive hardware verification system enables users to verify and debug advanced FPGA designs faster and with higher quality for greatly improved time-to-market, and realize more reliable and predictable results. Learn more about GateRocket online at www.gaterocket.com and sign up for a free webinar.

February 23, 2010 – Cortus is pleased to announce uCLinux for the APS3 family of processors. This version of Linux is ideally suited to low power, high performance, embedded systems. The APS3 family of processors are modern, powerful processors, specifically designed for embedded systems, featuring a tiny silicon footprint. 

The APS3 architecture is ideally suited for uCLinux. The clean, uniform, architecture means that the ported kernel code is straightforward, easily implemented and understood. There are no hidden pitfalls due to inconsistencies in the architecture which could reduce performance or trip up unwary programmers. Developing application programs is uncomplicated and creating drivers for new peripherals and hardware is simple.

Thanks to the rational design of the APS3 and close coupling of the compiler developer team and hardware engineers the port employed very little assembly code, in contrast with most other ports, whilst retaining all performance and features. This means that the port is easy to understand and the development of additional drivers is facilitated.

An example of the advantages of the APS3 architecture is shown by the efficient implementation of system calls. By taking advantage of the “trap” instructions and flexible register set most system calls pass parameters without using the stack or external memory – ensuring no cycles are wasted.
For more details see www.cortus.com/index.php?page=linux 

Mike Chapman, CEO of Cortus, said “We think that this must be the smallest ever CPU core running Linux. We are delighted to be able to offer a cost effective solution to our customers who require the power of the Linux operating system for their sophisticated applications. Using our core gains silicon space and power consumption and now with more operating system choices, our processor cores are a perfect fit with operating systems and this port allows our customers to provide a high quality, simple to use, solution to their customers.” 

The Cortus APS3 is a 32-bit processor designed specifically for embedded systems. It features a tiny silicon footprint (10k gates, the same size as an 8051), very low power consumption, high code density and high performance. A full development environment is available, which is available for customization and branding for final customer use. The ecosystem around the APS3 is rich and well developed, it includes a full development environment (for C and C++), peripherals typical of embedded systems, bus bridges to ensure easy interfacing to other IP and system support and functions such as cache and memory management units. For the most demanding designs the APS3 can be used in a multi-core configuration. The APS3 processor core is currently in production in a range of products from security applications to ultra low power RF designs.

About Cortus S.A.:

Cortus S.A. is the price/performance leader for 32 bit processor IP for embedded systems. Cortus cores are used in applications where one or more of small silicon footprint, low power consumption, good code density/small code memory size and high performance are important. The Cortus APS3 was crowned “the King of Lilliput” by the Microprocessor Report in May 2009.
http://www.cortus.com