Achieving Low BER Across 10+ Gbps Serial Links

by Kevin Morris

As serial data rates increase beyond 10 Gbps to address high-bandwidth applications (e.g., 40G/100G systems), board design challenges grow as well. Ensuring statistical reliability of a serializer/deserializer (SerDes) channel requires careful board design, as well as advanced silicon capabilities to handle losses due to PCB material properties and reflections due to discontinuities in the channel. In this webcast, we will discuss some of the solutions available to address these challenges and ensure high reliability for serial links at data rates beyond 10 Gbps.

In this 25-minute webcast, you’ll learn how to:

Address system challenges at high data rates
Incorporate advanced FPGA silicon solutions to increase system reliability
Increase productivity with advanced PCB tools and models

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Sponsored by Siemens Digital Industries Software

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Achieving Low BER Across 10+ Gbps Serial Links

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