feature article
Subscribe Now

Analog Devices and Your Digital BFF

Circling silently beneath the murky waters of the Gulf of Mexico, a solitary fin breaks the surface; then two, then three. Panicked swimmers paddle for the shore, anxious to distance themselves from the threat. Watch out! It’s a Blackfin!

Yankee chipmaker Analog Devices has released a school of Blackfin chips, causing mayhem in parts of Texas. These once-placid waters were TI’s territory. Now that dominance is under threat as a newer and hungrier challenger threatens to take a bite out of the market leader.

Meanwhile, back on dry land, we have three new processor chips to consider. They’re called the Blackfin BF500 family, and they’re brand new today. They’re cheap ($5 to $13 in quantity), they’re fast (300-400 MHz), and they come in three flavors.

The whole Blackfin family, which includes more than a dozen members, mixes 32-bit RISC with DSP programming. It’s a hybrid MCU/DSP that’s been gaining popularity for about a decade. Most microcontrollers are lousy at signal-processing code, and most DSPs are hard for the average embedded developer to program. Blackfin merges those two programming models with a processor that looks more or less like a typical CPU or MCU and can be programmed in C, but that also understands about coefficients, FIR filters, and butterflies. Blackfin isn’t the only chip family to do the CPU/DSP mashup, but, along with TI’s MSP430, it is one of the most popular. 

Let’s Meet the New Contestants

The three new chips are melodically named the Blackfin BF504, ’504F, and ’506F. Depending on which particular chip you prefer, you can get it with on-chip flash memory and/or a 12-bit ADC (analog-to-digital converter). In all three cases, the processor runs at 400 MHz, which is pretty lickety-split for a $5 chip. (I’m liking this Moore’s Law thing.) Blackfin processors all have dual MACs, too, so you can theoretically crank through 800 million multiply-accumulate operations every second.

Two of the three chips come with a big 4MB block of internal flash memory. The capacious internal flash is a good thing, because it’s all you’re getting. The BF500 chips have no external-memory interface, so you must run your code from the chip’s own internal memory. That’s not to say the chips have no external interfaces whatsoever; they do. You get a controller for removable memory cards, for example, which is handy for configuration storage, security keys, or whatever else you want to stash in an SD or CompactFlash card.

You also get 16KB of internal instruction SRAM, another 16KB of instruction cache, yet another 16KB of data SRAM, and still more 16KB of data cache. Finally, there’s 4KB of general-purpose scratchpad SRAM for whatever. For the chips that have internal flash, it’s fast enough that you can (and should) execute directly from it, but the instruction SRAM and cache allow you to download patches, create self-modifying code (yikes!), or just play around. If your code fits in 32 KB of SRAM and you have a way to load it at boot-up time, you can dispense with the on-chip flash and save a few bucks.

If you’re into heavy metal – and who isn’t – you get a pair of PWM (pulse-width modulation) controllers for line-power control or 3-phase motors. Y’know, the kinds of motors that swing heavy robot arms, turn big drums, or spin washing machines – that kind of stuff. There’s also a CAN (controller-area network) port provided, so your BF500 can talk to all the other BF500s strewn about your shop floor. All three variations of the BF500 include the now-standard set of cheap peripherals such as SPI, I2C, UARTs, timers, general-purpose I/O pins, and so forth.

Analog Devices has sensibly provided a cheap development kit for Blackfin, this one with the cutesy name of EZ-Kit Lite. It retails for just $199, so it comes in under most engineers’ signing authority without alerting the boss. Like most development boards, it has lots of connectors, jumpers, and DIP switches for fiddling and tinkering.

Chip packages don’t usually get a lot of attention, and the 120-lead LQFP package for these chips seems pretty normal. That is, until you flip it over and look at the big silver pad on the underside. It’s both a heat sink and an analog ground connection, and it needs to be soldered to your board. You can’t just ignore it. That strikes me as a manufacturing challenge most embedded developers haven’t dealt with before, but Analog Devices says it’s no big deal. Just be sure to route a big ground pad under the center of the chip and reflow your solder carefully. Once it’s soldered down, don’t expect the chip to ever come back off the board.

Survival of the Fittest

Despite the company’s name, Analog Devices sells mostly digital chips. Sure, it got its start making DACs and op amps, but nowadays it’s a full-line microcontroller and DSP vendor. Sort of like Texas Instruments, which doesn’t really make instruments.

The comparison with TI is a common one, and a source of irritation around Analog Devices (which now prefers to call itself ADI). TI is the de facto shark patrolling the DSP waters, while ADI is a relative barracuda: fast but not as big. Shout “DSP” in a crowded theater and most people run for Texas, not Boston. TI’s MSP430 product family has more or less defined the DSP/microcontroller concept for many engineers.

But that doesn’t necessarily make the MSP430 a better choice than Blackfin. ADI’s new BF500 chips have faster clock rates, dual MACs, and more internal memory than their nearest competitors (according to ADI). They also have more accurate (although slower) ADCs, which you’d expect from a company with “analog” in its name. That also explains the big metal grounding pad under the package. The BF504F and ’506F also have a ton more flash memory than TI’s equivalent parts, which makes the Blackfin chips both cheaper and smaller. And they have a cooler name.  

Leave a Reply

featured blogs
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Shift Left with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens investigate the details of Calibre’s shift-left strategy. They take a closer look at how the tools and techniques in this design tool suite can help reduce signoff iterations and time to tapeout while also increasing design quality.
Nov 27, 2023
639 views