Some dreams die hard. While digital FPGAs, structured ASICs/gate arrays, and other such configurable chips are commonplace, an analog equivalent remains a vision as yet unrealized to the same extent. Sure, there have been attempts – Actel has devices on the market, although the content is primarily digital; Lattice even tried once upon a time, but without leaving a clear mark. Standard FPGAs have increased their analog content with high-speed I/O circuitry, but that’s all carefully hand-crafted, with a narrowly controlled range of options from which the user can choose.
Analog has a number of things working against it when it comes to programmable arrays of any sort. The mix of what to put on there is a good start: you can’t just assemble transistors and allow them to be connected by the user; you’d never get the required performance. So you have to build higher-level blocks – and then, which ones and how many of each? Another challenge is the variability of leading-edge process nodes – it plays havoc with analog; such processes lend themselves much more to tender loving manual design. Letting an end user configure an array on such a process just feels like folly.
Finally, let’s just face it: analog is hard. Analog designers are a special breed: they resist designs done by computer, and for good reason. There’s a fair bit of the black magic that only a human can bring to the design. According to Cadence’s John Stabenow, users have more or less rejected analog synthesis. Even when it does well enough to do the job required and meet the specs, designers still aren’t comfortable with the aesthetics of the layout – which speaks to the subtlety that imbues analog design.
So when Triad Semiconductor perpetuates the analog array dream with the audacity to bring configurable analog arrays to market, they have to be aware that they’re following in some big footsteps that have led nowhere in particular. And presumably have taken steps to alter the path in a more profitable direction.
Triad is largely a design house; they do custom designs for their clients. The evolution of that led them to a via-configurable technology that would allow them to interconnect blocks of analog and digital circuitry using only a single via layer. They configured their first array, the VCA-1, themselves through independent product planning. But their other offerings all have their roots in specific custom engagements.
When asked to do a design, if they thought there might be more customers for a slightly more general version of a design being requested, then (presumably with customer approval) they’d do a superset of the specific customer spec and offer it for general sale. This is how they addressed the question of how much of what to put on a chip: each of the subsequent devices has been targeted towards a different problem, and their custom engagements point the way.
The analog blocks are hand-designed and routed; it’s only the higher-level interconnect that the user can manage. This is intended to address process variability to a large extent: most of the effect of the variability is within the block, so that a well-designed block will accommodate variations and isolate that from the users. The range of blocks extends from simple op amps of various flavors to band-gap generators and ADC/DACs. Voltage tolerance can be as high as 50 V. They haven’t tackled RF yet, although that’s on the roadmap.
The analog also coexists with digital, from 9,000 to 76,000 gates, and, on the Mocha line, with an ARM Cortex core and on-chip EEPROM and SRAM. The idea with Mocha is that you can take numerous sensor inputs, condition them in the analog domain, digitize them, and then make decisions and take actions in the digital domain, all on a single configurable chip. As you would expect (and hope), they claim to have taken pains to ensure that the analog and digital sides of the chip are isolated from each other. The vias can also be used to configure the pinout, both at the signal and power level.
Any sort of technology like this naturally bears the burden of tools. Let’s not even attempt to try to chronicle the ill fates of the numerous programmable logic would-bes that ignored the importance of tools, thinking that superior (or cheaper) silicon would absolve them of the need to sully their hands with software.
Triad also has tools, albeit schematic-based, as would be expected for analog. For validation, users can do a pre-layout simulation, a post-layout simulation, including full parasitic modeling, or SPICE-level simulation. But their clientele are largely domain experts, not so much design experts. So Triad’s experience is not so much one of turning the tools over to a customer and having a customer hand back a via mask file; it’s more of a collaborative effort, and the projects blur the distinction between a user-configurable chip and a custom design.
Triad inherits another aspect of the legacy of programmable logic, even though the devices aren’t field programmable. Mask programmability means that you have a dedicated wafer and no field programming circuit overhead, but such an array is still going to be less cost efficient than a custom chip since it will clearly be left with unused array circuitry. And here we meet the tradeoff between time to market and die cost.
Everyone thinks they’re going to have a system go gangbusters; few ever do, so few can actually justify the cost of a custom chip. But everyone wants to know that there’s a straightforward path to a lower-cost option if their sales do bust wide open. Of course, this sounds familiar to any follower of PLDs since it’s a story that’s been told and retold through the long history of programmable logic. Anyone remember Monolithic Memories’ HAL (Hard Array Logic) versions of PALs? Same deal. And it underscores Altera’s HardCopy and Xilinx’s EasyPath strategies. All different ways of telling the customer, “if you need a cost reduction, we’ve got a way to do it.” Even if it does sometimes come with a snicker knowing that almost no one will exercise the option.
And so with Triad: if needed, they can go in and remove unused blocks and cinch things up tighter to get a smaller design. For the blocks that remain, the design is left unchanged, meaning that changes to the performance of the circuit should, in theory, result only from changes in the higher-level via interconnect. This reduces, if not eliminating entirely, the risk that a cost reduction will screw things up.
It feels like there’s a lot of “what’s old is new” and “what’s new is old” going on here. But there also seems to be a fair amount of realism in not trying simply to mimic the hands-off nature of traditional programmables and having more of an assisted approach. The downside of that, of course, is that the business becomes less scalable – you’ve got to have more bodies to support more projects. But when your fundamental approach to business is through services, that can’t feel too bad; the chip business can drive the services business (like the original IP model before IP vendors got tired of that).
And so the dream of configurable analog remains alive. We’ll have to check back to see whether Triad’s attempt gets more traction than those that went before and how it fares compared to Actel’s Fusion devices. Triad is less audacious in its business model, but more audacious in the amount of analog it provides. Whichever way you look at it, given the history, this particular dream requires audacity.
Link: Triad Semiconductor
