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Package Creep

It seems so often that, here, in this space, we end up reflecting: “It used to be so easy.” Taking yet another example, once upon a time, you had packaging engineers – mechanical engineering types – who took care of all the packaging stuff. They told you how big to make your bonding pads, and that was about it. Oh, yeah, and the pesky ESD stuff. (Does it have to be all the way to 2000 V? Can we change the model so it’s easier?) The mechanical engineers lived off someplace different, and most electrical engineers never had to talk to them. It used to be so easy.

Life got a bit more complicated with the advent of flip-chip allowing bumps in an array instead of just the periphery. But things are getting even more interesting these days. TSV and other technologies are allowing 3D stacking of dice, and one immediate impact is that we don’t need as many strong drivers on the chips. It also provides more degrees of routing freedom, which is the point of the Pathfinding project.

But new ideas are increasing the encroachment of packaging considerations on both the IC design side and the PC board side. It’s getting harder and harder to draw solid lines where the packaging disciplines begin and end. It’s less and less obvious… is it a packaging issue or a chip design issue?

One alternative to TSV, but with a similar goal, is to use inductive coupling to get signals from one chip to another. In fact, work has been done placing pairs of transmitters and receivers above and below each other as a means of transmitting signals from chip to chip. A CICC paper by a team from Keio University in Japan illustrated some of the subtleties of this approach.

Pairs of transmitters and receivers can be configured, via enable signals, as transmitters or receivers – or as both – for the purposes of acting as a repeater getting signals up several chips. The problem is that, if you are trying to send a signal up the stack, and you use a transmitter to send to the receiver above it, you’re also sending to the receiver below – unless you use a shield, which is the conventional solution, and which requires extra power.

Keio proposed to get around this by using a three-coil solution. With a choice of three coils on any layer, you could always ensure that you can have a receiver either directly above or below the transmitter, but not both. This means you can get rid of the shield and lower the power. The cost, of course, is the extra coil.

They proposed a coil configuration that they referred to as an “XY coil.” They “hide” the coil in the other logic by creating a square loop and putting the X and Y lines on separate metal layers in and amongst the other lines being routed for logic. This required a bit more power (but apparently less than that of the shielding) and greatly reduced the size of the coils. But let’s back up a second here: this is a die-to-die interconnect issue, and here we are burying circuits in the die to make them as small as possible. Is it a package issue or a chip design issue?

This is still pretty early work; not addressed was how you would keep such a stack cool. Which is the perennial question for 3D packaging and a question that was also outstanding last year in a lot of the TSV discussions. Typically people would throw around the likelihood of metal interposers for heat dissipation; there was lots of shoulder-shrugging in that “someone will figure it out” way.

An ICCAD paper by a team from National Taiwan University provided some insight into one approach to this that works for TSV but would not work for inductive coupling: the use of microchannels for cooling. Imagine the material between dice being grooved boustrophedon-style so that a fluid (either liquid or gas) can enter on one end, zigzag back and forth between the dice, and exit the other side. The catch is that you have several such layers and one fluid flow – and the fluid gets from one layer to another by its own TSVs. Which is why, unless they figure out how to couple fluid inductively from one layer to another, this requires the TSV approach.

The problem they were trying to solve was the thermal calculation. From a simplistic standpoint, you’ve got fluid entering a multi-layer stack, being heated as it enters, and, before that bit of fluid can be cooled down again, it has to flow through the entire stack, picking up more heat as it goes, until it finally emerges out the other side and, with a micro-sigh of relief, can start cooling down again. From a calculation standpoint, if the fluid was just standing still, you’d have heat transfer by convection and conduction; add flow to it, and now you’ve got this plume moving through the grooves as what they refer to as the “thermal wake.” That’s such a cool term; it practically makes you want to go surf it.

While that exercise was intended specifically to determine the physical thermal characteristics – back in the realm of mechanical engineering – this also translates into design considerations, including signal and power integrity. Such analysis is typically done on a chip basis, but, in one example of tools taking on the package/chip encroachment, e-System is planning to release a version of their SI/PI analysis tool this year that handles TSV and takes thermal effects into account. This extends such analysis from the chip level to the entire stack of chips. So… is it a packaging issue or a chip design issue?

On the other side of things, folks at Georgia Tech have been working towards what Prof. Rao Tummala calls “system on panel” or SoP (also decoded as “system on package”). This more or less pushes the interface between silicon and a PC board further down the hierarchy.

More traditional approaches to this idea had multiple dice and passives embedded in an organic substrate, much like a PC board. Of course, a point of mechanical stress is the interface between silicon and FR-4 (or whatever organic is used). So each die/organic interface is subject to thermal stresses as the temperature changes. One solution to this is to change the material from organic to silicon; now the dice and the substrate expand and contract together.

More discussion with GT’s Madhavan Swaminathan (also CTO at e-System) reveals that, with older fabs already paid for, it becomes tactically economically advantageous to take advantage of them to build these SoPs.

The deal with SoPs is that you can use standard silicon processing techniques to build an entire module, including multiple dice and passives, in a single quasi-monolithic unit. Passives and filters are actually built into the silicon and can be buried in internal layers. On top of that structure are placed the dice.

Of course, the thermomechanical issues don’t entirely go away; you still have to mount this larger silicon structure on a PC board. But you’ve reduced the amount of interconnect subject to such stresses, since much of what would have come out onto the organic material stays interconnected within the silicon module.

Building one of these things again requires integrated chip and package design, and there are currently no tools available for handling that. It’s still a research topic, so presumably there’s time for the tools to materialize. But, here again, the question arises: is it a packaging issue or a chip design issue?

Packaging seems to be insinuating itself both into the chip and PCB realm. It may no longer be so easy to keep those mechanical types cloistered off in some other building out of sight.

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