Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints

by Kevin Morris

Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices’ reprogrammability to validate hardware and software. Once the design is ready for volume production, certain types of ASICs help the designers meet power, performance, and cost targets. This paper discusses the evolution, architecture, and capabilities of Altera HardCopy ASICs as a package- and pin-compatible FPGA counterpart that is ideal for taking designs into volume production.

Author: Larry Landis, Senior HardCopy Project Manager

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Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints

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