SAN JOSE, Calif. – December 07, 2009 – CEVA Inc, [(NASDAQ: CEVA); (LSE: CVA)], a leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the industry’s first integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox^TM Software Development Environment, the Application Optimizer allows application developers to easily develop software for CEVA’s DSPs purely in C-Level, eliminating any hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs.

Substantial Performance Advantages Over Other Licensable Solutions

With the addition of the Application Optimizer, the enhanced development environment for CEVA’s DSP cores dramatically simplifies the software development process and improves the absolute performance of the target application. As an example, using the standard AMR-NB (Adaptive Multi Rate compression, narrow band) vocoder C reference, the CEVA-X1622 DSP core required just 19 MHz when compiled out-of-the-box (for worst-case frames and streams). In comparison, other licensable solutions require more than 45% higher speed for the same out-of-the-box compiled code.

Algorithm OOB C code * C-optimized * Assembly optimized * Competitor’s OOB C code
AMR-NB 19 MHz 15 MHz 12.5 MHz 27.7 MHz
G.729AB 13.7 MHz 10.3 MHz 8.7 MHz N/A
* Numbers relate to worst-case frames and streams, using standard ITU / 3GPP C reference code

Vastly Reduced Software Development Time

With the growing complexity of designing a modern SoC architecture, the burden of embedded software development poses the greatest challenge for IC vendors. The effort involved in writing and optimizing software for a given multifaceted system architecture has become the largest bottleneck in the design cycle. The Application Optimizer toolchain along with a number of other key elements in the CEVA-Toolbox^TM Development Environment, shifts the software design flow to pure C-level and reduces the burden of architecture-specific know-how traditionally required by application developers.

“With today’s highly integrated chip designs and the growing complexity of programming these advanced processors, development tools are now the key item for DSP selection,” said Will Strauss, founder and president, Forward Concepts. “The addition of a comprehensive end-to-end C level software optimization toolchain for CEVA’s DSP cores offers a significant advantage to customers designing DSP applications, eliminating the tedious and time-consuming requirement for Assembly-level optimization.”

Key Elements of the Application Optimizer include;

Project build optimizer: Creates optimized build configurations, simulates and profiles multiple application scenarios based on the customers application and exact system conditions
DSP and Communication Libraries: C-callable assembly optimized functions, significantly improve performance and development time of DSP and communication applications.
Application Profiler: A cycle accurate C-level application and memory subsystem profiler
Scoring based compilation: Results in less than 1:1.5 ratio between out-of-the-box C to optimized assembly
Other integral elements of the Application Optimizer include; post linker optimizer, debugger connectivity for easy migration of algorithms (e.g.: MATLAB), test environment automation.

For more information on the Application Optimizer and CEVA-Toolbox^TM Development Environment, visit www.ceva-dsp.com/Toolbox

Development Tools and Support

CEVA’s DSPs are supported by a robust Development Environment that includes software development tools, development boards, software system drivers and RTOS. The Development Environment is built upon thousands of man-years of knowledge, accumulated since the inception of CEVA’s first DSP core in 1991. CEVA’s tools and support have been leveraged by thousands of engineers worldwide to produce more than one billion CEVA-powered chips that have shipped to date. The development tools run on Windows and Linux, and are supported by a worldwide customer service team. CEVA DSPs are further complemented by extensive algorithms and applications from CEVA and the CEVAnet third-party development community.

About CEVA, Inc.

Headquartered in San Jose, Calif., CEVA is a leading licensor of silicon intellectual property (SIP) DSP Cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA’s IP portfolio includes comprehensive solutions for multimedia, audio, voice over packet (VoP), Bluetooth and Serial ATA (SATA), and a wide range of programmable DSP cores and subsystems with different price/performance metrics serving multiple markets. In 2008, CEVA’s IP was shipped in over 300 million devices. For more information, visit www.ceva-dsp.com

MOUNTAIN VIEW, Calif., December 7, 2009 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Hisilicon Technologies Co., Ltd., a worldwide provider of ASICs and solutions for communication network and digital media, and a subsidiary of Huawei Technologies, has established Synopsys as its primary EDA partner across its implementation and verification design flows. Hisilicon has signed an expanded business agreement to extend its use of Synopsys’ IC Compiler place-and-route technology and DesignWare(R) IP as well as other tools from the broad spectrum of Synopsys’ Galaxy(TM) Implementation and Discovery(TM) Verification Platforms.

“Since its founding, Hisilicon has carefully selected the key strategic partnerships that help us deliver high quality ICs and services to our customers,” said Teresa He, vice president t of Hisilicon Technologies Co., Ltd. “We chose to partner with Synopsys because of their technology and proven ability to help make us successful.  By helping us deploy advanced technologies such as the VMM verification methodology and advanced chip synthesis to improve design and verification productivity, Synopsys has reinforced our confidence in its short- and long-term technical leadership.”

“Within a relatively short period of time, Hisilicon has established itself as one of the premier fabless IC design companies in China, and we are grateful to play a supporting role in their success,” said John Chilton, senior vice president of marketing and strategic development at Synopsys.  “By increasing their usage of Synopsys tools, IP and services, Hisilicon will be able to continue to aggressively focus on bringing differentiated network communications and digital media silicon solutions to market.”

With this expanded agreement, Hisilicon has broad access to tools and IP from Synopsys, including the Galaxy Implementation Platform’s IC Compiler place-and-route technology, DC Ultra(R) RTL synthesis, DFTMAX(TM) compression, Formality(R) power-aware equivalence checking, PrimeTime(R) SI signal integrity analysis, PrimeTime PX power analysis and StarRC(TM) parasitic extraction; the Discovery Verification Platform’s VCS(R) with MVSIM voltage-aware simulator and HSPICE circuit simulator, and MVRC voltage-aware static rule checker; System Studio algorithm design and analysis; and DesignWare(R) IP for PCI Express 2.0, SuperSpeed USB 3.0 and DDR2/3.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated  portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.