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Xilinx Strengthens Its Defenses

New FPGA Families for Mil/Aero

Designing for military and aerospace applications can be tough sometimes. The other designers – you know, the ones that do commercial applications – can have the pick of any cool technology they want to use. If some new femtowatt terahertz nanodollar FPGA rolls off the fab line, those commercial designer kids can grab it and go. You, on the other hand, have to stick with only devices that are certified, proven, specially packaged, and … old. It’s like they’re going out on dates in their Dad’s new Porsche or Ferrari while you can either drive your own Citroen deaux chevaux vapeur or borrow your brother’s yellow 1972 AMC Pacer.

Mil/aero design certainly carries special technical challenges.  The high reliability operation required for equipment operating in life-or-death situations demands a completely different approach than coming up with something that can successfully stream YouTube to our smart phones.  In addition to high-reliability operation, mil/aero equipment often has to operate in harsh environments – with hazards like extreme temperature ranges and radiation, and security is, of course, a central concern.  

Beyond these technical hurdles, there are legal and administrative issues.  Devices have to have the appropriate pedigrees and documentation in order to even be considered for use in many mil/aero applications.  Often, the perfect technology exists to solve your design problem, but it hasn’t got the requisite acronym string in its meta-data showing that it’s been blessed by the appropriate governing gurus, so you are left to invent your own solution out of DO-953-approved paperclips and bailing wire.

The applications mil/aero designers are creating, however, are anything but pedestrian.  Mil/aero applications often have enormous technical hurdles to overcome in areas like signal processing performance, power consumption, weight, and footprint.  The combination of high technical demands and lagging access to leading-edge solutions can paint designers into a corner where they have to deliver the best solution with the worst technology.

In the FPGA domain, there have always been specialized devices available for military and aerospace use.  Beyond these, commercial off-the-shelf (COTS) initiatives have allowed some mainstream commercial devices to be used for some applications.  For the most part, however, the FPGA options available to the mil/aero crowd have lagged considerably behind.  

Now, Xilinx has introduced its new Virtex-5Q family of FPGAs for the aerospace and defense industry.  This brings 65nm, high-density, high-performance, feature-rich FPGA technology within reach of many mil/aero design teams.  Now, there are more DSP blocks for complex signal processing, more on-chip memory for embedded applications and caching, more LUT fabric for integration, and less dynamic power consumption for power-limited systems.  Basically, all the things that excited the rest of the design world about high-end 65nm FPGAs can now be exciting to the mil/aero crowd as well.

This is fabulous news for people designing everything from secure communications systems to electronic warfare.  Each new generation of FPGAs brings with it a higher level of design that can be done without resorting to obscenely expensive low-volume ASIC projects.  In a defense application, you are almost always far ahead to use an FPGA if it meets your performance, power, and integration requirements.  Most of these projects have such a low production volume that the cost of using an ASIC is completely dominated by the NRE charges – which are substantial for an ASIC in the “an FPGA can’t do this” range.

Since we’ve talked in depth about the capabilities of the Virtex-5 family already, let’s look at what’s new and different with this announcement.  First, Xilinx has added the additional packaging, temperature range, and documentation required to put their “military-grade” stamp on the offering.  Also new for Xilinx is a process for ordering bare dice.  In many applications, die stacking, multi-chip modules and other packaging techniques require the use of bare dice, and FPGA companies have always been extremely hesitant to sell them.  Now, by making this option available, sophisticated customers can do things with FPGAs that they’ve never been able to achieve before.  Additionally, since the devices are logically the same as the company’s commercial devices, development teams can prototype with commercial devices and swap in the (more expensive) defense-grade versions in production.

Xilinx has also partnered with other vendors to provide implementation support for avionics designers in meeting standards such as DO-254.  The availability of services from a provider that is familiar with the qualification and documentation requirements can be a major help in getting projects completed, and the judicious use of such third-party services can actually have a significant schedule- and cost-reduction impact on many projects.  

Perhaps most interesting of all, however, is the introduction of a single-chip crypto (SCC) solution.  When Xilinx rolled out their Virtex-6 and 11.1 development environment recently, they also began touting a concept called “Targeted Design Platforms.”  The idea behind these platforms is to provide much more than a simple development board, IP library, or reference design.  For specific applications, the company is putting together near-complete solutions including devices, development hardware, tools, IP, reference designs, and documentation that get you somewhere around that magic “80%” level.  Buying a solution that includes most of the basic work already done allows your team to focus specifically on the “value added” portions of the design and on customization areas where standards are in flux or where the solution may be required to mate with a number of other components with different interface standards.  This essentially amplifies the advantages of choosing a programmable logic solution in the first place, as you can concentrate your efforts primarily on the design where FPGA flexibility comes into play.

The SCC solution is one of the first of these Targeted Design Platforms to be announced.  While Xilinx has previously offered single-chip crypto capability, the new platform combines all the elements into one pre-packaged solution.  This should take a lot of the messy guesswork out of the crypto part of many applications, allowing development teams to focus on the real problem rather than re-inventing crypto for the zillionth time.  

While this latest announcement focuses on aerospace and defense, we can also see hints of a trend in how Xilinx may be marketing their solutions in the months and years to come. We expect to hear less FPGA-speak and more domain-specific solution language coming from the company, combined with more, and better-differentiated, IP and software aimed at bringing the flexibility of FPGAs out to more non-FPGA design projects.  

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