feature article
Subscribe Now

Cadence Uses the F Word

FPGA PCB Co-design Debuts

Mentor brought us Leonardo, Precision, ModelSim, and Catapult. Synopsys sells Synplify and HAPS. Magma brought us Palace and Blast FPGA. Big EDA companies have had anything from a toenail to a whole leg dangling in the FPGA pool for years now… except Cadence.

Like a politician skillfully skirting a controversial issue, Cadence deftly danced around the FPGA domain without touching – one big boot in the IC/ASIC design world, and another firmly planted at the board/system level – with the word “FPGA” never crossing their lips.  When you were designing a board with your Cadence tools, you could put all sorts of parts down – ASICs, standard parts, ASSPs, analog… you know – anything, really.  

Now, all that seems to be changing.  This week, Cadence announced a new addition to both their OrCad and Allegro PCB design suites – “FPGA System Planner.”  There!  They said it!  And, it’s even the first word in the title.  Cadence has partnered with Taray (whose 7Circuits tool we’ve discussed here before) to produce an integrated upgrade to their PCB layout tools that smooths the flow between the FPGA and PCB design domains.  Cadence is not the first EDA company to swim these waters – Mentor Graphics had automatic pin data passing and fractured symbol support working between their FPGA and PCB tools years ago, Altium has seamlessly merged their FPGA/PCB design software into one big suite, and Synopsys(Synplicity) did some of the same things with their Certify tool almost ten years ago.

The Cadence Taray combination is compelling, however.  FPGA System Planner is sold as an upgrade to your PCB design software, and it provides what the company refers to as “synthesis” of FPGA pin assignments.  The really cool part of this process is that it doesn’t just facilitate communication between the FPGA tools and the PCB tools.  That’s been done already.  While it’s nice to have something more robust than a spreadsheet to pass I/O assignments back and forth, the Cadence solution goes far beyond that with a built-in understanding of the FPGA vendors’ pin assignment rules and a library of interfaces and protocols that goes considerably beyond the basic bus/bundle capabilities of most tools.

As we’ve discussed before, the problem in bridging these two domains is conflicting design constraints. To get the best timing and cleanest layout in the FPGA, we FPGA folks (and certainly our FPGA tools) consider only the part of the system that’s between the I/O pads.  The sweet-spot I/O placement can make the FPGA place-and-route tool’s job much easier, and problems like over-constrained critical timing paths can simply melt away if we are allowed to move around the I/O assignment a bit.  

When we hand that design over the wall to the board layout team, however, they have their own set of issues and constraints.  All of our differential pairs have to have matching routes on the board, of course.  Our parallel busses need to be length-matched for timing reasons, and our new multi-gigabit serial interfaces require special attention to signal integrity issues on the board and to the connectors. Often, when we bring an FPGA pin assignment into our PCB layout world, obvious problems show up immediately.  The “rats nest” criss-crosses the package, and even breaking the routes out of the FPGA space can be a major challenge – sometimes requiring more layers, often making routing difficult or even impossible, and frequently causing board-level timing or SI issues.  

For the board designer, the solutions to these problems may appear obvious at first.  “Let’s move this wide bus from the left side of the device to the right side, and all these pairs can float up toward the top near the connector.”  Unfortunately, without knowledge of the fact that some of those busses and control lines belong to the same peripheral interface, that insufficient power rails have been routed to the top of the device, and that moving other signals around will necessitate a cross-chip nightmare getting from I/O pins to hard-IP blocks on the FPGA and back – our board-specific suggestions back to the FPGA design may be ill-informed and unworkable.  

Cadence’s FPGA System Planner comes in two flavors – big and small.  The small version handles a single FPGA on the board and is compatible with the company’s OrCad suite of tools.  The high-end version can handle complex, multi-FPGA, multi-board designs, and it works with the Allegro tools.  On the high end, building on the success of Taray’s product, Cadence is pointing out that the tool is particularly useful in nightmare ASIC prototyping scenarios where dozens of very-high-pincount FPGAs may be involved in a single design.  In these cases, the cost of the boards can explode, with additional layers required to break out from all those FPGAs – skating between devices to get across the board or out to the connectors.  A tool like FPGA System Planner can have significant impact on both the design time and the cost and complexity of the boards in such designs.

Many design teams do their own logic design – including FPGA development — but outsource PCB layout to specialty houses.  FPGA System Planner will work for these scenarios as well, providing a clean, file-based interface between the domains that works well even when the teams are not co-located.  In these scenarios, the value may well be even higher, as working out design compromises cross-company can involve a lot more complicated communication than just walking to the cube next door and saying “Hey, mind if I move your bus around a bit?”

Whether Cadence will become fluent in FPGA parlance is yet to be seen.  Certainly, their HDL simulation tools are used in many FPGA designs, although they are primarily in large system houses where HDL simulation is standardized across a number of divisions or design domains.  Cadence’s PCB design tools have always been used with designs sporting FPGAs as well – as most board designs today contain at least one FPGA, and Cadence has a big chunk of market share in the PCB design world.  This announcement, however, is the first time Cadence has appealed directly to the FPGA design community with a high-value product that solves a real, FPGA-specific problem.  Yes, we know, the new offering is through a partnership and not primarily born of Cadence-developed technology; however, that does not disqualify them.  Remember, Mentor acquired Exemplar and Model Technoloogy, Synopsys acquired Synplicity, and Magma brought in A-Plus Design Technology to get them into (or more into) the FPGA game.  

For now, however, Cadence’s newfound vocabulary is a welcome addition to the party.  For design teams that depend on Cadence’s PCB capabilities, a significant improvement has just arrived that could shave giant chunks from project schedules and board manufacturing costs.  We can just hope that there are more announcements to come.

Leave a Reply

featured blogs
Jul 6, 2020
If you were in the possession of one of these bodacious beauties, what sorts of games and effects would you create using the little scamp?...
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

featured video

Product Update: What’s Hot in DesignWare® IP for PCIe® 5.0

Sponsored by Synopsys

Get the latest update on Synopsys' DesignWare Controller and PHY IP for PCIe 5.0 and how the low-latency, compact, power-efficient, and silicon-proven solution can enable your SoCs while reducing risk.

Click here for more information about DesignWare IP Solutions for PCI Express

Featured Paper

Cryptography: A Closer Look at the Algorithms

Sponsored by Maxim Integrated

Get more details about how cryptographic algorithms are implemented and how an asymmetric key algorithm can be used to exchange a shared private key.

Click here to download the whitepaper

Featured Chalk Talk

Smart Embedded Vision with PolarFire FPGAs

Sponsored by Mouser Electronics and Microchip

In embedded vision applications, doing AI inference at the edge is often required in order to meet performance and latency demands. But, AI inference requires massive computing power, which can exceed our overall power budget. In this episode of Chalk Talk, Amelia Dalton talks to Avery Williams of Microchip about using FPGAs to get the machine vision performance you need, without blowing your power, form factor, and thermal requirements.

More information about Microsemi / Microchip PolarFire FPGA Video & Imaging Kit