feature article
Subscribe Now

Tiny Tiny Chips

Actel Launches nano FPGAs

What do you get when you multiply a normal FPGA by .000000001?  Well, those of you that have been reading this publication for awhile may jump right in with the observation that this is a floating-point operation, and since FPGA math would normally need to be fixed-point, we will have to “quantize” before we get started.  Fair enough. 

As you also probably know, quantization is the process of approximating a vast range of continuous values by a comparatively small set of discrete ones.  We choose the range of values we’re most interested in and set things up so we have the most precision around that range of values.  For our discrete values, we’re going to choose power, size, and price.  (Experts: click here to launch into a rant about how we’ve just confused and misled tens of thousands of neophytes about how REAL quantization works.  What? The link doesn’t work?  Bummer.)  Now, we realize we’re pushing the limits of editorial discretion in our description here, but bear with us.

You see, Actel has just jumped into the market with this confusing factor of 10-9, and it is incumbent upon us to explain what the whole thing means.  “nano” as a prefix generally makes us think small – very small.  By the numbers, the new “nano” version of Actel’s flash-based IGLOO FPGAs have prices as low as 49 cents, static power as low as 2 microwatts, and package size as small as 3x3mm.  If that’s too big for you, you could go with “known good die,” where apparently Actel has bypassed the whole wafer process entirely and done the lithography directly on raw grains of sand.  OK, we’re kidding about that last part, but the die will indeed be very, very small.  Combine that size with the fact that flash-based FPGAs can be used with no on-board configuration circuitry and you have a definite record-breaker for the amount of board real-estate consumed by a fully-functional FPGA. 

The new family has densities ranging from 10k to 250k gates.  Yes, Actel still uses the somewhat inflated “system gate” as their density unit, but they’ve got a good excuse – their devices are not based on the traditional LUT-4 structure used by other manufacturers to define fabric capacity.  Of course, the other vendors no longer use LUT-4 either (they’ve graduated to wider basic logic elements) so maybe the argument is beginning to wear thin.  At any rate, these are small FPGA devices by today’s standards, but massive density is not the point.  You can still pack a surprising amount of useful capability into these devices with these densities.

On the power side (and this is critical if you’re using these devices in their sweet spot – as mobile and handheld battery-powered applications) the new nanos can operate from 1.2V to 1.5V core and I/O – giving you an easy sliding scale for performance/power tradeoff.  As with previous Actel low-power families, nano includes the single-pin-activated Flash*Freeze mode that shuts the device down almost instantly to an ultra-low power state without trashing the rest of the circuit by bad I/O behavior.  The 10K device has static power of only 2 microwatts, so the power you burn will be strictly related to the application you’re doing.  Actel’s Libero design tool suite also continues to add capabilities for estimating and optimizing power consumption, so these devices come with a robust arsenal of capabilities for minimizing power consumption.  If you use these capabilities correctly, you can minimize more than the FPGA power as well – these are ideal chips for system-wide power management and reduction.

Packaging options include the previously announced 8×8, 6×6, 5×5 and 4×4, as well as the new 3x3mm microchip-scale package.  The company is also launching a “known good die” program for you high-volume, cost-sensitive, size-sparing die-stackers.  Since Actel’s devices are single-chip (therefore single-die) solutions, your stack will be shorter for lack of a required commodity flash device for FPGA configuration.  Actel says they are already shipping KGD to a number of customers.

Actel has also announced the new devices at the extended commercial temperature range of -20C to 70C.  We figure they tested them in this range and they worked, so what the heck?  Why not have an extended temperature range?  In many portable/mobile applications, however, extended temperature ranges are important.  Consumers don’t tend to be too careful with keeping their portable GPS and satellite phone units all warm and cozy when they hike up north, and that’s just the tip of the iceberg in environmental challenges for mobile devices.

 The company is apparently aware of another major challenge for high-volume device manufacturers, and that is lead-time for component orders.  Actel is debuting a new program that allows essentially zero-week lead time for the new devices, maintaining a stocked, bonded inventory to allow immediate shipments.  For companies with tight manufacturing schedules and JIT inventory practices, reliable low-lead-time ordering can be even more important than price in saving manufacturing costs. 

Speaking of price, Actel is claiming that they now have over 50 product variants for under $1.  This is obviously a bit of marketing math mayhem – multiplying the number of sizes by the number of packages by, perhaps, the number of available colors of logo silkscreening…  We also don’t expect this fact to be on the top of the customer “wish” list either – “Dang, if only they had 60 variants under a dollar I’d design one in, but 50 just isn’t quite enough for my tastes…”  Kidding aside, it does show that the company is putting heavy emphasis on low-cost, high-volume applications such as those in the consumer market.  As we’ve discussed before, this is an entirely different market than the traditional low-to-medium volume FPGA pool.

As we have come to expect, the new devices are already supported in the latest version of Actel’s development tool suite – Libero IDE v8.4 SP2.  The package includes power-optimization, battery life estimation, and advanced power analysis features in addition to the usual, more pedestrian FPGA design capabilities such as simulation, synthesis, and place-and-route.  There is also a new starter kit – the “Low-cost IGLOO nano Starter Kit” — that will be available in November 2008.  The new kit includes the AGL250 nano VQ100 (that’s right, they sprung for one of the bigger devices with a lot of pins, even in the “starter” development kit) with development tools, tutorials, documentation, and all the other stuff you’d expect in a starter kit.

With this announcement, Actel is pushing full-speed into their previously-defined direction of low-power, high-volume, low-cost FPGAs for the masses.  While the dynamics of this market are not yet well established, the company does continue to distinguish and differentiate itself with its strategy and product offerings.  Time and the market will tell how well this strategy will pay off.

Leave a Reply

featured blogs
Apr 24, 2024
Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you'll find a community where employees share their perspectives and experiences. By providing a glimpse of their personal...
Apr 23, 2024
We explore Aerospace and Government (A&G) chip design and explain how Silicon Lifecycle Management (SLM) ensures semiconductor reliability for A&G applications.The post SLM Solutions for Mission-Critical Aerospace and Government Chip Designs appeared first on Chip ...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Achieving Reliable Wireless IoT
Wireless connectivity is one of the most important aspects of any IoT design. In this episode of Chalk Talk, Amelia Dalton and Brandon Oakes from CEL discuss the best practices for achieving reliable wireless connectivity for IoT. They examine the challenges of IoT wireless connectivity, the factors engineers should keep in mind when choosing a wireless solution, and how you can utilize CEL wireless connectivity technologies in your next design.
Nov 28, 2023
20,003 views