A few years ago when SERDES became available on FPGAs, they were exotic. Both for the FPGA guys and for their users. The FPGA guys had to learn how all this stuff worked, tune the (relatively) complicated analog circuits, and make it all function. Those were some of the last features to be officially released on those devices because they just took longer to get right. More than one customer was stranded waiting for parts with working high-speed I/Os.
Meanwhile, there weren’t a lot of customers who knew what to do with this stuff. The protocols were complex, and rolling your own took fortitude. And likely a stiff drink to steady the nerves. They looked to the FPGA guys for help, and the FPGA guys were looking to them for help. Gradually the FPGA guys got a handle on things and even defined their own lightweight high-speed serial protocols – Aurora for Xilinx and SerialLite for Altera. But the FPGA guys were scared to death of what customers might try to do – this collection of circuits could be put together in all kinds of scary demonic ways that may or may not have been intended. So they tried to limit the ways in which they could be used – essentially defining “sandboxes” in which customers could play. Go outside the sandbox, and you’re on your own – no support.
Consistent with this was the fact that I/Os with SERDES were available only on the highest-end devices – Stratix GX for Altera and Virtex 4 FX for Xilinx. This coupled them with the biggest densities, and, in the case of Virtex, tied them in with the built-in PowerPC processors. There were cases where customers were buying PowerPCs just to get the SERDES.
Things started to change with Virtex 5, when Xilinx’ Multi-Gigabit Transceivers (MGTs, the Xilinx brand for the fancy high-speed I/Os) became available on all three of the styles of Virtex – those with processors, those with DSPs, and those just intended for logic. This lowered the price point of the SERDES, although it was still limited to the Virtex family, which is still the high end.
Then Lattice shook things up with their EPC2M devices, which were intended to address the low-cost market by competing, not with Virtex and Stratix, but with Spartan (Xilinx) and Cyclone (Altera). And the Lattice devices included SERDES. This brought SERDES capability down to a much lower price point.
Altera followed by introducing the Arria family, targeted for a similar market. There are rumors that Arria is in fact Stratix remarketed, although it seems like they took the Stratix die and made some actual tweaks, shutting down parts of the circuit to reduce power. So while it might not be a Stratix die outright, it certainly isn’t a Cyclone device with added SERDES. But if the price is low enough, it kinda doesn’t matter. (It just allows us to whisper conspiratorially, “Ya know what they’re REALLY doing?”)
So now there were two low-cost families making SERDES available. It came as a curious bit of news, then, when Avnet announced a small daughter card with a National SERDES chip on it that could be used with Spartan devices on Avnet’s boards to couple Spartan with SERDES. Could this be Xilinx and Avnet’s answer to ECP2M and Arria?
In short, no. Avnet readily acknowledges benefits to both on-chip and daughter-card SERDES – it depends on what you’re doing. Using an on-chip SERDES has some obvious upside – less chip space, fewer signal integrity issues associated with getting signals between the FPGA and the SERDES, and more functionality in the I/O – the FPGA I/Os tend to be programmable, yielding configurations not possible with the Avnet solution. On the other hand, apparently the power supply design is easier with the off-chip SERDES. You don’t need the low-impedance tantalum decoupling caps, and the 2.5-V and 3.3-V power supplies can be shared between the FPGA and SERDES. With the on-chip SERDES, a separate isolated supply is required for the I/Os. The National SERDES can also drive farther on a cable than the built-in SERDES can, or can drive low-cost cable, so for more environments where being extra fussy about the signaling isn’t desired, the two-chip solution can be better.
If the big complex protocols like PCI Express and Serial RapidIO are being used, the on-chip SERDES should be used. The daughter card solution supports only a couple I/Os, and it might be possible to put some higher-layer logic in the FPGA, but it wasn’t really intended to be used that way. You can implement Aurora using the Avnet solution (but not SerialLite – duh!)
The daughter card being used by Avnet is their own EXP card format. In concept, it’s pretty much the same as the FMC card we discussed a couple weeks ago. In fact, Avnet was aware of the FMC standard developing, but they needed a solution sooner than would be possible if they waited for the details of the FMC to be sorted out, so they made a strategic decision to go with their own proprietary format. Whether they migrate to the industry-standard FMC in the future is officially TBD, so their official position now (and for any reasonable future) is that EXP is their solution.
So, in the end, the Avnet solution is not a strategic answer to a product line, but rather is a targeted offering for users of their prototyping boards. Their EXP format allows the interfacing of different I/O types on the boards, and this particular EXP supports SERDES outputs. It’s useful for implementing simple chip-to-chip or proto-board-to-proto-board signals requiring only a signal or two (although it could drive cables as well). It’s not intended to be a general SERDES solution, and it isn’t intended to drive backplanes and other heavier-duty pieces of infrastructure such as would be involved in industry-standard protocol implementations.
Altera and Lattice don’t appear to feel threatened by it, either. Of course, they’ve got the “obvious” positioning that one chip is always better than two. That may in fact not be the case for all applications, but they are showing no signs of concern. And in fact, while Avnet has been a steadfast partner to Xilinx, this appears to be an Avnet deal, not a Xilinx-by-proxy deal.
So the remaining question is, when will Xilinx do a Spartan-with-SERDES?!