feature article
Subscribe Now

Bigger and Better Storage

Last week’s ISSCC and DesignCon conferences included presentations of developments in non-volatile memory, and we present some highlights here. Some of the papers discussed developments in novel cell types; others addressed improvements in more well-adopted technologies. So first let’s review the different kinds of non-volatile cells being covered to set some context.

The lives of a cell

Flash is the best known of the technologies; it’s the one that the least technically savvy of us might actually go out and buy ourselves. But there are actually two flavors of flash that are typically used for different applications. To understand how we got where we are, we have to go back to the first commercially viable erasable non-volatile solid-state memories: EPROMs. These used a FET with a floating gate between a control gate and the channel. “Floating” meant that it wasn’t connected to anything, so any charge that ended up there couldn’t go anywhere. From the standpoint of the control gate, the presence or absence of electrons on the floating gate changes the VT of the transistor, giving a straightforward way to read the cell: when the control gate is asserted, either it conducts or it doesn’t.

Electrons are put on the floating gate using a process called hot electron injection. This is done by running a large current along the channel of the transistor. Think of it as whitewater rapids: the energy and turbulence cause some splashing out of the riverbed. In other words, some of the electrons have enough energy to splash up and punch through the oxide barrier into the floating gate. Once there, they have no energy left and are stuck.

And that was actually part of the problem: how the heck do you get them down from there to erase the device? UV light could energize them enough to jump back down through the oxide and rejoin their brethren in silicon, so the original devices had windows and required long erase times under UV bulbs. Long exposure to velvet paintings of Jimi Hendrix under UV light might be entertaining, but sitting around waiting for memories to erase isn’t.

The answer to that was EEPROMs. They work by a very different mechanism, using quantum tunneling to get the electrons through a very thin barrier oxide. The process, involving an applied voltage that narrows part of the energy barrier during programming to allow controlled tunneling, is called Fowler-Nordheim tunneling. It works in both directions, so you can program and erase with it. This has evolved into today’s NOR Flash (so-named based on the arrangement of cells, which resembles a CMOS NOR gate). It can be written and read byte-by-byte with random access, making it suitable for code store, but it is slower to program, and the arrangement doesn’t provide for the smallest die area per bit.

Which is where NAND Flash comes it. It’s actually a combination of the old UV and EE technologies (and was originally simply called Flash). It uses hot electron injection for moving electrons onto the floating gate, but, instead of the UV light, it uses Fowler-Nordheim tunneling for erasing. Because the hot electrons have a distribution of energies, some can get trapped in the oxide layer. If these build up over time as the device is programmed and erased over and over, they can essentially neutralize the cell. This wear-out mechanism gives NAND Flash few write/erase cycles (i.e., lower endurance) than NOR Flash (although there are management techniques to make that pretty much irrelevant in most common applications). It’s programmed and erased in blocks, making it faster to program, and it uses much less area per bit, so it is better suited for mass storage where random access isn’t required.

More recent developments allow the more careful placement and sensing of charge on the floating gate, allowing more subtlety than simply on or off. These multi-level cells (MLCs) can provide more than one bit’s worth of storage in a cell by allowing the amount of charge to be sensed in levels. A two-bit MLC cell has four levels. This adds complexity and programming time, but it provides an obvious capacity boost.

A somewhat more exotic flavor of cell is the NROM cell made by Saifun. This uses a nitride layer instead of a floating gate. During programming, carefully arranged charge packets are placed at the two ends of the nitride gate. This keeps electrons away from most of the gate oxide, meaning you don’t get the trapped electrons there, giving these cells high endurance. Each of the two charge packets is effectively a bit, so one cell can store two bits.

Another unusual memory is phase change memory (PCM). The storage element on this memory uses the same kind of glass used on DVDs. It’s what’s called a chalcogenide glass, which sounds like a nasty disease, but is actually a glass formed with chalcogens, which sound like some form of pond scum, but are actually a fancy name for elements from Group VI in the periodic table. Most typically used is a Germanium-Antimony-Tellurium alloy – Ge2Sb2Te5, or GST. This glass can, using heat, be changed back and forth from the crystalline to the amorphous phase. On DVDs, it’s the optical characteristics that are used; in PCM it’s the change in resistivity. One issue is the fact that environmental heat can erase the memory. So, for example, you can’t buy a pre-programmed PCM and then solder it onto the board, because the heat of soldering can erase it.

Finally, there is still life in the antifuse world. Way back in the day, metal fuses once dominated programmable elements, and, like the fuses in older houses or in your car, they worked by either conducting or getting “blown” to break the fuse. Antifuses came along and worked in reverse: they’re normally open and then are “blown” to create a short. Both fuses and antifuses are irreversible: once programmed, they can’t be erased. While, for many everyday activities, that might sound like a bad trait, it’s actually an excellent trait if you’re in a harsh environment that might flip bits in an erasable technology. Antifuses have been most commonly used in some PLDs, notably from Actel and QuickLogic, although eFuses are a newer form of antifuse being used to provide tunability in large ICs.

With that background in place, let’s talk about the developments discussed last week. Most of these were announced at ISSCC; one was discussed at DesignCon. We present highlights only; further details can be gleaned from the respective proceedings.

Are these geometries too tight?

Intel presented a 45-nm 1-Gb MLC NOR Flash device that uses a self-aligned cell structure to reduce the cell size, improve reliability, and eliminate coupling between floating gates on adjacent wordlines; the die size is 30 mm2. Even though they feature the cell structure, it is but one of several changes made to address the increased delicacy of doing MLC programming and sensing at this node while maintaining decent programming time (5 MB/s).

Meanwhile, Toshiba and SanDisk presented a 16-Gb MLC NAND device built on 43-nm technology with a die size of 120 mm2. They had to take special measures to mitigate the increased effects of gate-induced drain leakage (GIDL) at this process node. Another notable thing they did was to provide a separate connection for a lower I/O VCC so that the I/Os could talk to other surrounding low-voltage devices while using a separate higher VCC internally. This kept them from having to build much larger and more expensive charge pumps to boost up the lower VCC to the high voltages still needed for programming.

Keeping it on the level… or not

SanDisk pushed beyond the current 2-bit MLC NAND Flash to a 3-bit MLC device. This means that the programming and sensing have to be able to distinguish eight different charge levels (including the erased state). The specific chip they showed was a 16-Gb device made on a 56-nm technology; it had a die size of 142.5 mm2.

Saifun showed a four-bit NROM device. This basically takes their original NROM cell, which is already a 2-bit-per-cell structure, and adds MLC capabilities to each of the two bits, doubling the capacity. A 1-Gb memory made on 45-nm technology was 30 mm2.

ST Micro and Intel showed a PCM memory that adds two partially-crystallized states to the existing fully-crystallized and fully-amorphous states. This creates a 2-bit-per-cell MLC capability, as demonstrated in a 256-Mb device at 36 mm2 using 90-nm technology. It’s interesting to see a modern circuit that actually has a bipolar PNP transistor in it. I can’t decide if it makes me feel old or young again.

Overcoming writer’s block

Programming time has clearly been an issue for the larger devices. As they are migrated onto smaller geometries, and as more levels are added to the cells, changes are being made in the programming schemes to speed up the time it takes to program.

One change made by SanDisk was to go to all-bitline programming. Traditionally MLC NAND devices are programmed in two halves, first programming odd bit lines, then even. This keeps bitlines from cross-coupling and incorrectly programming cells; the unused bitlines act as shields. But you have to do two programming steps instead of doing it all at once. In addition, neighboring cells affect each other, meaning that the sensing of a cell programmed in the second wave will look different, depending on whether or not its neighboring cell was programmed in the first wave. SanDisk presented a chip that programs all bit lines in parallel, eliminating the two-step process.

Another focus for speeding up programming is parallelization. Older methods load data, program, load more data, program, and so on. The mechanisms for MLC programming are even more complex. SanDisk made the programming and loading of data more independent so that new data can be loaded during programming of other cells, and that, together with their all-bitline approach, achieved 34 MB/s programming in a 16-Gb unit. Micron and Intel included a synchronous double-data-rate (DDR) interface in addition to a traditional flash interface. This, combined with careful interleaving of internal operations while shuffling data around, got them to 100 MB/s programming and 200 MB/s read/write in an 8-Gb unit.

Gotta keep ‘em separated

Renesas addressed the issue of Flash wear-out by creating a dual-channel structure that has one channel for programming and one for reading. The benefit is that any trapped charge created during programming (which uses hot electron injection) is away from the read channel, so the read fidelity isn’t affected. (Much.) Both channels are used when erasing; because erasure uses Fowler-Nordheim tunneling, it doesn’t have the same trapping effect as hot electrons do.

Going 3D

Samsung presented a two-layer MLC NAND Flash chip made on 45-nm technology. Note that this is two layers of two-bit MLC. That is, effectively, two chips stacked on top of each other. There are a number of ways to approach the 3-D process. Memory bits using polysilicon can be built, but they’re very slow. It’s also possible to physically stack dice; that’s not the approach taken by Samsung. They use a single-crystal silicon methodology, which grows new silicon on top of an existing die, typically using epitaxy, but there are also methods that deposit amorphous silicon and then irradiate it into a single crystal. Samsung didn’t specify how they actually grew the second layer.

They used two layers only, but claim that the process could be used for 4-5 layers, 3-4 layers being optimal. One significant challenge is boring holes down through the layers so that they can all be interconnected, something that could only get tougher with more layers.

Antifuse lives

I was honestly surprised to find that a DesignCon paper titled “Evaluating Embedded Non-Volatile Memory for 65 nm and Beyond” was about a new antifuse technology. Sidense presented their new 1.5-T cell, which essentially squishes a control transistor and a thin-oxide capacitor together to form a very small cell that they claim can be used in technologies from 180 nm to 45 nm and below. The focus of this technology is, of course, in secure applications where reverse engineering needs to be avoided and where bit integrity is paramount. Sidense doesn’t sell a specific memory chip but rather has created this cell for licensing to designers that need such cells.

Logical extrapolation?

All of this makes me wonder whether any of the folks making FPGAs with non-volatile cells will take advantage of any of this stuff. Pure speculation on my part; all is quiet on that front, but ears are tuned.

Leave a Reply

featured blogs
Apr 19, 2024
In today's rapidly evolving digital landscape, staying at the cutting edge is crucial to success. For MaxLinear, bridging the gap between firmware and hardware development has been pivotal. All of the company's products solve critical communication and high-frequency analysis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Advanced Gate Drive for Motor Control
Sponsored by Infineon
Passing EMC testing, reducing power dissipation, and mitigating supply chain issues are crucial design concerns to keep in mind when it comes to motor control applications. In this episode of Chalk Talk, Amelia Dalton and Rick Browarski from Infineon explore the role that MOSFETs play in motor control design, the value that adaptive MOSFET control can have for motor control designs, and how Infineon can help you jump start your next motor control design.
Feb 6, 2024