Pushing programmable logic into portables is a power play. Portable devices put power consumption at a premium, and silicon vendors looking for a socket have to answer for each and every coulomb consumed by their chips. Of course, they’re also interested in absolute minimal cost and board real estate, so getting a programmable device into your portable is unlikely at best.
Now, Altera’s somewhat uncategorizable Max II family is adding a super-stingy “zero power” (meaning “not very much power”) Max IIZ version to the lineup. Altera is not the first to go nello on power with their FPGA/CPLD marketing. They’re just resurrecting the ruse used by companies like Philips and Lattice Semiconductor a few years back (apparently, the “zero power” term comes from dropping below the milliamp threshold of older ammeters with microamp devices and getting a reading of zero.) While we’re not necessarily buying into the whole “zero power” concept, it is nice to have a device with very, very low static power consumption so that you’re not draining batteries while doing nothing. By the way, in our old math book, anything to the “zero power” equals one.
When we say that Max II is uncategorizable, we mean that it is in a somewhat unique position with regard to its marketing and architecture. If you plopped one of these babies under a microscope, you’d see some black plastic magnified thousands of times. But, if you took one out of the packaging and looked at the architecture on the die, you’d see something that looks suspiciously like a non-volatile SRAM-based FPGA with a configuration flash memory embedded. Altera doesn’t make non-volatile FPGAs, however. They make SRAM-based FPGAs and CPLDs.
If you zoomed in on the marketing materials with a microscope, you’d see Altera calling Max II a CPLD, despite the obvious lack of the traditional macrocell CPLD architecture. Max II designs like a CPLD, however, and is used in places you’d use a normal CPLD – plus a few more. It runs faster than a typical CPLD and has higher density… kinda’ like maybe an FPGA, almost. For now, we’ll play along, though. Let’s pretend Max IIZ is a CPLD and it uses zero power. (Insert fine-print here about microamps, quiescent current, ambient temperatures, and stuff.)
When Altera compares Max II against “competing devices,” they’re most likely talking about families like Lattice Semiconductor’s MachXO (another device family strolling down the avenue with one foot on the CPLD curb and the other on the FPGA street) or Xilinx’s Coolrunner-II (a CPLD family made up of actual CPLDs and, coincidentally, historically rooted at Philips where the “zero power” debacle began over a decade ago). One might also compare them against devices like Actel’s “Igloo” family of flash-based FPGAs, however, because the density, capability, and power consumption are at least in the same league. In fact, Igloo might make an even better comparison.
By the numbers, Altera’s new family has two members – one at 240 LEs and one at 570 LEs (these are actually FPGA LUT4s, but we won’t tell – outside parentheses anyway), which are equivalent to 192 and 440 “typical macro-cells,” respectively. For comparison purposes, Lattice’s MachXO ranges from 256 to 2280 LUT4s, Xilinx’s Coolrunner-II has from 32 to 512 macrocells. What’s the big deal about that? Doesn’t it sound like the new Altera family is right in the middle of the already-established competitive products? Well, yes and no. While the density may be just about average for a CPLD of this class, the FPGA architecture is quite a bit more area-efficient than a CPLD macrocell structure. As a result, Altera can slip larger devices into smaller packages, giving more gate density per board area – an important consideration for mobile devices. Altera’s smallest (5X5) package integrates a lot more logic and I/O than a macrocell device of a similar size.
Comparing with the Actel offering is a bit closer. Actel’s Igloo is available in a 4×4 package, and the versions of the device that can go in that package are closer to the new Max IIZ in density. Actel’s package uses a very fine .4mm pitch on pins, so you’d better have your board fabrication process under control if you’re headed that way.
Looking at power consumption, we see that the dynamic power ramp is much better than a typical CPLD. This isn’t surprising, because the average internal connection on an FPGA is driving a much smaller capacitive load than in a CPLD. Regular non-zero Max II has had great dynamic power for years when compared with conventional CPLDs. That’s one of the reasons they built it that way.
The thing that’s new here – and what makes Altera come out with the “zero power” marketing terminology — is the micro-amp quiescent current – twenty-nine of them, to be specific. This is the amazing accomplishment of Max IIZ. Why? Let’s take a look under the hood. We mentioned earlier that Max IIZ is an SRAM FPGA with flash-based configuration memory built in. That means it should take quite a bit of current just to keep the fabric configured. Altera has cleverly reduced this quiescent current into the low micro-amp range with the new family, putting it on equal (or maybe even a little better) footing with macrocell CPLDs when the clocks are not wiggling.
Max IIZ should let portable designers use CPLDs the way non-portable designers have used them for years – as cheap employment insurance. You design your system and everything is looking good until, at the last minute, a requirement arises that you somehow overlooked, or your device needs to connect to a newly emerged standard, or… you get the picture: a potentially career-limiting design limitation is discovered at the last minute. No problem; you pull the ripcord on the emergency CPLD and it comes alive and solves your problem – providing that missing SD interface, bridging voltage levels on I/Os, whatever is required to keep you employed and in good standing with engineering management.
Altera says that tools are available now, and silicon will be available in Q1, 2008. The EPM240Z M68 is estimated at $1.25 in volumes of a million or so. At that kind of price, I’d sprinkle a few on every circuit board like a garnish. It’s good insurance.