Using CPLDs to Replace or Augment Microcontrollers
With the advent of low-power CPLDs, electronic product designers now have new options for implementing many of the functions traditionally performed by microcontrollers. This article discusses several ways design scenarios that are advantageous to use a CPLD instead of a microcontroller, and when it makes sense to use a CPLD as a companion to a microcontroller.
Tell a group of portable electronics designers that there is a low-power digital device that allows them to use a software program to reconfigure the operation of the hardware, and nine out of ten will likely assume that it is some form of microcontroller. This is understandable. With a vast array of features and packages, abundance of software development tools, and huge library of application code, the ubiquitous microcontroller has found a home in nearly every type of portable application. However, with the arrival of low-power CPLDs, designers now have new options for implementing many of the functions traditionally performed by microcontrollers.
This article examines when it is advantageous to use a CPLD instead of a microcontroller, and when a CPLD makes a good companion to a microcontroller. The examples offered are grouped into three categories, based on function and level of complexity. The first category is I/O management, focusing on pin-level applications. The second category is port management, with the emphasis on the various interfaces between devices. The third category is system management, for applications that use a pin or port to control system-level functions.
Designers who are new to programmable logic will find many aspects of CPLD design to be similar to designing with traditional microcontrollers. A simplified description of CPLD design flow is:
- The design is written in a high-level language, such as Verilog or VHDL, using a software development tool.
- The design is simulated for functional correctness.
- The design is “fit” to a particular CPLD, providing the physical aspects such as resource utilization and timing paths.
- The design is simulated for timing correctness.
- The design is programmed into the physical device.
One major difference is the availability of sophisticated in-circuit emulators for microcontroller check out. However, once the nuances of the programmable technology are understood, microcontroller designers do well with CPLD design.
Examples of CPLDs Replacing Microcontrollers
The following offers several of the many applications where a CPLD can cost-effectively replace a microcontroller.
When considering whether to use a CPLD or a microcontroller for I/O management, the quantity and the type of I/Os needed are two critical considerations. Microcontrollers enjoy a reputation as small and inexpensive, and certainly, there are many small, inexpensive microcontrollers from which a designer can choose. However, if an application requires a large quantity of general-purpose I/Os, often a CPLD can be cost-competitive with a microcontroller. Small, inexpensive microcontrollers are usually limited to a serial port and, at most, a few general-purpose I/O pins.
Designers discover that microcontrollers with dozens of I/Os are no longer so small and inexpensive. On the other hand, CPLDs tend to be I/O intensive; it is not uncommon for a small form factor CPLD to have well over 50 I/Os. An example would be the Altera MAX IIZ EPM240Z CPLD in a 5-mm-by-5-mm package with 80 I/Os. In addition to enjoying an I/O quantity advantage, in general, CPLDs are more flexible than microcontrollers. With some exceptions, the majority of CPLD I/Os can be used for any purpose.
Programmable Level Shifting
Many products require the use of logic devices of varying voltages. To support multi-voltage applications, designers frequently need to connect devices of differing voltage levels. This is rarely possible with a microcontroller that has a limited number of I/O resources, which often operate from one voltage source. In contrast, CPLDs have a larger number of I/Os, which are grouped into multiple banks. Each I/O bank, in turn, is assigned a unique voltage source. Thus, creating a voltage-level shifter is merely a matter of grouping all the I/Os of one voltage in one bank and connecting the associated voltage reference to the power rail needed for those I/Os, as shown in Figure 1. While it is useful to be able to accomplish level shifting using a CPLD, an even greater advantage is derived from the power of programmability combined with the level shifting. For example, suppose an application calls for a LCD display that is not supported by the host processor and is not at the same voltage level. A CPLD could be used to provide voltage-level shifted timing control between the host processor and the LCD display.
Figure 1. Using a CPLD to Perform Voltage-Level Shifting Pulse Width Modulation
Often, a designer chooses a microcontroller for a specific function, such as pulse width modulation (PWM). This too can be accomplished using a CPLD. In PWM, the time period of the square wave is kept constant, while the time the signal remains high is varied or modulated. Thus, the duty cycle (tON) of the signal can be varied. PWM provides a powerful method for controlling analog circuits in a digital system. One method that is common in portable applications is using PWM to vary the intensity of an LED.
CPLDs do not have dedicated PWM circuitry, yet it is not difficult to implement a PWM output. A CPLD that contains an internal oscillator can be used as a source for the frequency, and counters can then be used to modulate this frequency.
Designers often choose a microcontroller for its analog-to-digital converter (ADC) capabilities. However, in certain cases, such as keypad decoding, an ADC may not be necessary.
Figure 2 shows a basic switch array and an ADC. A set of resistors is connected in series between VCC and GND, and a switch is connected to each resistor tap and a common node. If a switch is activated, the circuit generates a voltage proportional to the switch location in the resistor stack. To be used in a digital system, this analog signal must be converted to digital value, and often a microcontroller is chosen because it has a built-in ADC.
Figure 2. Analog Key Pad Array
However, a CPLD is also an option. With the addition of a simple, low-cost external capacitor, the CPLD can use the internal oscillator, Schmitt trigger I/O, and high-density arithmetic-programmable logic fabric to accomplish the analog-to-digital conversion.
Some CPLDs such as Altera MAX® IIZ devices are optimized for many system management functions such as power sequencing, which includes multi-voltage system power up and system reset, as well as chip-select generation. These two applications are often integrated into a single non-volatile, instant-on device. Multi-voltage system power sequencing requires a device to be instant on and ready to manage the power-up sequencing of other devices on the PCB. Therefore a CPLD, which powers up within microseconds, is a better choice for power sequencing than a microcontroller, which often needs milliseconds to power up.
Figure 3 illustrates a typical CPLD device power sequencing application. As board density and the number of power planes on a board increases, the complexity of the power sequencing also increases. CPLDs can easily manage the power sequencing for all levels of system complexity. Multiple power rails support different devices, and control logic is needed to manage the complete power-up sequence of each device. To ensure that accidental driving of these signals does not occur during power up, this CPLD is also used to control critical bus signals until the power up is complete. The JTAG port monitors the power sequence, storing errors and information upon power up. It can also be used to set break points in the power sequencing, which is useful during the debug phase.
Figure 3. Power Sequencing Using a CPLD Watchdog Timer
Many system management applications require some form of timer. Designers may be surprised to discover that a CPLD can be used for many of the timer functions that are usually associated with microcontrollers. With a few discrete capacitors, resistors, diodes, and metal-oxide-semiconductor field-effect transistors (MOSFETs), a simple but powerful resistor-capacitor (RC) timer-based circuit can be built that power up the CPLD at regular intervals. In the example circuit in Figure 4, the RC values are selected to create a 10-second timer. This basic timer can be extended by three external capacitors (C1, C2, and C3), which are used to create a simple non-volatile binary counter. Thus, an interval period from 10 seconds to 80 seconds can be fully implemented in this CPLD, utilizing 19 percent of its logic.
Figure 4. Building a Timer-Based Power-Up Circuit for a CPLD
Examples of CPLD and Microcontroller Companionship
A CPLD does not always compete with a microcontroller. Following are several examples where a CPLD makes an excellent companion to a microcontroller.
GPIO Pin Expansion
In a common application known as general-purpose I/O pin expansion, many designers combine the programming capabilities of a small, inexpensive microcontroller with the general-purpose I/O resources of a CPLD. The CPLD builds a set of internal registers that can be accessed by the microcontroller through any available serial port, such as I2C or SPI (see Figure 5). This allows the microcontroller to use existing I/O resources to expand its total I/O count. With this expanded I/O count, designers can use the CPLD for voltage-level shifting, which increases the utility of the CPLD.
Figure 5. GPIO Pin Expansion
Portable application designers often find a need to connect devices with differing I/O interfaces. This function is often referred to as bridging because a CPLD is used to form a bridge between dissimilar interfaces. This section describes three such cases:
- Serial to serial – I2C to SPI
- Serial to parallel – SPI devices (serial) to a host processor (parallel)
- Parallel to parallel – host processor to Compact FLASH+ (CF+)
In each of these examples, there are reasons why a CPLD would likely be a better choice than a microcontroller. For one, there is often a need for more I/Os than is cost-effectively available in a microcontroller. A microcode implementation may not be functionally able to meet the necessary performance of the interface. In addition, the implementation may be far more burdensome to implement in microcode than in CPLD hardware.
Figure 6 illustrates how a CPLD can be used to bridge between two differing serial interfaces: I2C and SPI. This design can be implemented in this CPLD, using about 43 percent of the available logic and six I/O pins.
Figure 6. I2C to SPI Interface Using a CPLD
Figure 7 shows a host processor interfaced to a SPI master, using a CPLD to implement this serial-to-parallel interface. This example creates a host-processor bus interface and a complete SPI master, and can be implemented in this CPLD using about 30 percent of the available logic and 25 I/O pins.
Figure 7. Host Processor to SPI Interface Using a CPLD Parallel-to-Parallel Conversion
In Figure 8, a CPLD is used to bridge between two different parallel interfaces. This example implements a host processor bus interface to a CF+ device. It can be implemented in this CPLD, using about 54 percent of the available logic and 45 I/O pins.
Figure 8. Host Processor to CF+ Interface Using a CPLD
Traditionally, some form of microcontroller has been the only “programmable” logic available to the low-power electronics designer. However, with the introduction of low-power CPLDs, designers have new options for portable applications. This article highlighted multiple examples of how a low-power CPLD can be used in portable applications to replace or augment functions traditionally implemented in microcontrollers. As a result, low-power electronics designers have another set of problem-solving tools for portable applications, as well as a vastly superior ability to choose optimal devices when creating innovative new products.