feature article
Subscribe Now

Space FPGAs Get a Boost

Actel Announces Improvements

Actel has announced a significant round of enhancements to their space-bound FPGA families, including a new, power-efficient line called RTAX-SL.  Before we jump into those announcements, let’s have a brief discussion on what happens when we put tiny little space helmets on our FPGAs and launch them into orbit.

FPGAs and spacecraft would seem like a match made in the heavens.  As you might guess, spacecraft are far from mass-produced.  Developing a custom chip such as an ASIC for a satellite can result in astronomical unit prices by the time you amortize the non-recurring engineering (NRE) startup costs over the tiny spacecraft unit volumes.  Also, once in orbit, spacecraft are either impossible or prohibitively expensive to service.  If a change is needed to hardware operating in space, your options are extremely limited.  Software changes, on the other hand, can be accomplished with a comparatively simple upload. To round out the picture, many space applications have an enormous appetite for computing performance at a very high power efficiency – the classic case for hardware acceleration.

If this sounds to you like an ideal environment for FPGAs, you are at least partially right.  With no NRE, and (usually) in-system reprogrammability, and the ability to blast out spectacular levels of custom-hardware performance on a tight power budget, why wouldn’t we just load up our spacecraft with as many FPGAs as they could carry and sort out the details later?  Our costs would be dramatically lower than for custom ASIC devices, we’d be able to re-program even the hardware parts of our system in orbit, and our signal processing and switching tasks could be extremely power efficient, saving those expensive solar arrays for other jobs on the ship.

The big spoilers of this beautiful plan are, of course, tiny little neutrons.  Most FPGAs (more on the “most” in a minute) hold their configuration in SRAM-like memory structures.  An errant neutron striking the right place can flip a bit in those structures, effectively changing anything from routing to lookup table logic to memory and register contents.  Of course, there are neutrons flying around here on the ground as well, but the chances of your FPGA getting toppled by one of these “single event upsets” (SEUs) increases exponentially as you move out of the protection of the atmosphere.

Two approaches have been attempted to break this problem.  One, employed by Xilinx in their space FPGA family, is to work to mitigate the radiation effects on SRAM-type FPGAs.  Strategies for SEU mitigation include packaging, triple-module-redundancy (TMR) logic generation, and constantly reading back, checking, and re-writing FPGA configurations to detect and correct SEU corruption quickly when it happens.  While this strategy is often just fine for payload electronics, many flight-critical systems require more immunity to transient events.

The second approach to putting FPGAs in space is that employed for years by Actel – create FPGAs that don’t depend on memory-like cells for their configuration.  Unlike SRAM-based FPGAs, anti-fuse FPGA devices create metal-to-metal connections that define the configuration.  This approach is a compromise, bringing to the table one big downside and several uncomfortable compromises.  The big downside is that we lose one of our reasons for picking FPGAs in the first place.  As you might guess, the metal-to-metal connections of anti-fuse FPGAs are not reprogrammable.  Once you burn an SRAM FPGA, it is burned for life.  There will be no on-board reprogramming.  Dang.

OK, now that we’ve mourned the loss of in-system reprogrammability, what do we get in return?  Lots of pretty cool benefits, actually.  Since we’re not relying on transistors to create the routing paths, the configuration of these devices is radiation immune.  Neutrons may be able to flip the charge in your SRAM cells, but it can’t bust the metal-to-metal connections in anti-fuse FPGAs.  That means the only thing we have to worry about protecting from radiation are our remaining memory elements – registers and RAM.  These are protected by a variety of schemes from TMR to cyclic redundancy checking (CRC).  Also, ditching all those configuration transistors makes our devices faster, and not having to feed them constantly to keep our FPGA alive saves a bundle of power. 

Actel thinks it doesn’t save quite enough power, however.  In space, power is one of the most precious commodities.  Every bit of power your device consumes must be collected by expensive (and heavy) solar cells.  That power also requires bigger conduit, more cooling, and beefier power transistors – the chain goes on and on.  Each of these elements also adds weight, and in getting into space, weight is money.  Another thing that adds weight is external configuration logic.  SRAM FPGAs have it, anti-fuse doesn’t.  The board area, solder joints, and extra chips won’t be missed.

To address the power issue, Actel is announcing a new family, the RTAX-SL.  The company says that SL has approximately 50% lower standby current than previous generations.  RTAX-SL is based on the same architecture as the company’s popular (in space, at least) RTAX-S.  Lower power can save us a bundle in cost.

Speaking of cost, these parts are not cheap.  While they’re far, far less expensive than custom ASIC devices, they still would scare the spectacles off the accountants in most purchasing departments accustomed to commercial FPGAs.  Since these FPGAs are one-time programmable, that gives us another problem to deal with – development and prototyping.  With regular, garden-variety (you grow programmable logic in your garden, don’t you?), reprogrammable FPGAs, you can use a development board with an FPGA hard-soldered on and re-program it every time you find a bug during development. 

With anti-fuse, however, you don’t want to be throwing away a one-time programmable device with quite a few more zeros in the price tag every time you make a typo in your HDL.  In conjunction with Aldec, Actel offers a prototyping solution based on Actel’s re-programmable flash-based ProASIC3 FPGAs that allows you to make mistakes to your heart’s content without filling your lab’s waste bin with enough bogus silicon to finance a new house.  Once you’ve gotten past the training-wheel stage and killed the obvious bugs, you can move on to prototypes using commercial-footprint versions of the Axcelerator (AX) compatible FPGAs with the same basic silicon as the flight-qualified FPGAs, but without the flight-qualified price tag.  This means you can save the big-bucks, space-qualified, no-mistakes-allowed integration for last.

Actel says that they have also increased the qualification level of their testing process for flight-qualified devices to QML Class V.  This means that the devices are approved for use in even higher-reliability systems than before, including command and data-handling systems, telemetry, attitude, and station-keeping tasks.  While this improvement may seem boring (Sorry QA engineers of the world, we’re just kidding.  Really.), it does help in the continuing campaign to address the black eye that Actel came home with several years ago when they got in a playground fight with some re-fusing anti-fuses. 

Space (and military-aerospace in general) FPGAs have always been a significant portion of Actel’s business, and they represent the only area where the company has a dominant market position.  With all the recent emphasis on the commercial flash-based products, it is good to see that the company still has a significant focus on their long-time strength.

Leave a Reply

featured blogs
Dec 6, 2023
Optimizing a silicon chip at the system level is crucial in achieving peak performance, efficiency, and system reliability. As Moore's Law faces diminishing returns, simply transitioning to the latest process node no longer guarantees substantial power, performance, or c...
Dec 6, 2023
Explore standards development and functional safety requirements with Jyotika Athavale, IEEE senior member and Senior Director of Silicon Lifecycle Management.The post Q&A With Jyotika Athavale, IEEE Champion, on Advancing Standards Development Worldwide appeared first ...
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Analog in a Digital World: TRIMPOT® Trimming Potentiometers
Sponsored by Mouser Electronics and Bourns
Trimmer potentiometers are a great way to fine tune the output of an analog circuit and can be found used in a wide variety of applications. In this episode of Chalk Talk, Patricia Moorman from Bourns and Amelia Dalton break down the what, where, how, and why of trimpots and the benefits that Bourns trimpots can bring to your next design.
Feb 2, 2023