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Unified FPGA-ASIC Design Flow Provides Designers Versatility in Meeting Production Goals

Today’s fast-paced chip delivery schedules require that logic designers employ design flows that are versatile enough to take advantage of several implementation technologies. Specification changes, pricing or yield issues, and production ramps can change the target implementation technology for a design. Designers might be required to change FPGA devices or vendors, or move their designs from prototyping in an FPGA to production with an ASIC.

Making a decision on whether to use FPGAs or ASICs is based on several requirements including performance, power, unit volumes and time to market. In some cases, FPGAs are used to get the product to market before competitors, and then converted to ASICs during production ramp. Extremely high-performance or low-power designs usually mandate the use of ASICs. In production runs exceeding 50,000 units, ASICs have a low per-unit cost. However, this equation may be changing. Rising capabilities and shrinking price points are making FPGAs an increasingly viable alternative to ASICs for complex designs and larger production runs.

For example, according to industry research, ASIC design starts will decline to fewer than 4,000 in 2006, while FPGA design starts hit 90,000 in 2002 alone. Many of these starts no doubt follow the path from design to prototype to production. As FPGAs encroach upon the ASIC domain for both production and prototyping, the line between FPGA and ASIC designs has blurred to the extent that designers now seek the capability to use an FPGA for one project, and then switch to an ASIC for the next.

To achieve this, a single environment and tool flow is required that can re-use as much of the designers’ work as possible. This solution would enable both FPGA and ASIC implementations while delivering the most efficient results possible by providing an easy migration path for designers to switch between each technology.

The Requirements of a Versatile, Comprehensive FPGA-ASIC Design Flow

A versatile, comprehensive FPGA-ASIC physical synthesis flow can help designers meet often-stringent production schedules. This flow should facilitate design migration and combine an integrated device model within an automated flow that features timing analysis and ASIC-strength synthesis and optimization into a single tool.

A fully integrated, detailed device model would be used to guide optimizations throughout the synthesis process. Since design requirements vary greatly, FPGA designers need the flexibility to go for either push-button results or manually decide on the range of design optimizations to perform. Such a solution should also provide analysis capabilities throughout the entire design cycle that can help designers make these decisions.

In order to enable easy migration to ASICs for design implementation, this technology should be fully automated and feature ASIC physical synthesis and analysis. Full automation empowers ASIC designers to quickly meet their design’s timing with minimal area and power. This solution should feature FPGA architecture-specific RTL synthesis, along with concurrent timing analysis, all in a single tool. Utilizing these leading-edge technologies, this solution would deliver results in a single-pass flow driven by the designers’ timing constraints. This capability can relieve designers from performing repeated iterations in the most time-consuming implementation step, resulting in greater productivity.

This next-generation solution also could meld ASIC-strength synthesis technologies with architecture-specific optimization capabilities. This would provide FPGA designers with access to ASIC-grade capacity and high-level, architecture-independent optimization algorithms early in the design flow, while leveraging FPGA physical synthesis technology later in the design flow to deliver optimal results. Unlike traditional FPGA synthesis tools, this solution would deliver highly optimized FPGA implementations and significant performance improvements without manual user interventions, floorplanning or iterations. A common front end also could help provide an environment for smooth migration between FPGA and ASIC implementations.

Integrated ASIC-strength analysis capabilities should be included to allow designers to view schematics and generate reports at every stage of the design flow. Since physical synthesis results correlate better with final implementation timing numbers, a timing analysis engine would give designers early insight into the problem areas in the design, before going on to the FPGA vendor’s place-and-route stage. Cross-probing between timing, schematic and HDL views would allow designers to quickly identify and fix problems earlier in the design cycle.

This next-generation FPGA-ASIC physical synthesis solution would facilitate design migration with the use of “golden” source files featuring both HDL source files and timing constraint (SDC) files. The HDL source files could be technology neutral and infer data path components such as RAMs, multipliers and DSP blocks instead of instantiating them. This would allow optimal mapping even if the target technology changes, without requiring source code modifications.

This solution also could feature gated clock conversion and data path element inference for FPGAs to ensure that ASIC designs prototyped on FPGAs are implemented optimally. Gated clocks could be converted to clock enables, and finite state machines and arithmetic data path units could be extracted and optimally mapped to make best use of modern FPGA resources. With a single design environment for their FPGA designs, designers using this solution could quickly migrate their designs from one FPGA to another if necessary, or to ASICs.

This next-generation physical synthesis solution could be specifically designed to take advantage of advanced FPGA architectures, utilizing leading-edge technologies such as multi-clock retiming, fan-out optimizations, device-specific resource mapping and constraint-driven placement planning. Such a solution would bring ASIC-strength synthesis technologies to FPGA designers.


ASIC designers are increasingly turning to FPGAs for production or prototyping. In turn, with the ever-increasing size and complexity of next-generation FPGAs, FPGA designers require ASIC-strength tools to help them achieve design goals in the shortest time possible. Today’s logic designers must employ an automated, fully integrated design flow versatile enough to be used for both FPGAs and ASICs.

Blast FGPA, a fully automated RTL-to-FPGA physical synthesis solution from Magma Design Automation, provides the versatility of advanced capabilities and turnaround time designers need. Benchmarking has shown that Blast FPGA boosts performance 15 percent, when compared to the conventional FPGA synthesis flow. Moreover, Blast FPGA’s unique area optimizations reduce area by 10 percent. Blast FPGA provides designers the confidence that they can easily migrate their design to another FPGA or an ASIC according to their specific production specifications.

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