He pauses for exactly the right amount of time, then whips into his delivery with energy and zeal – “Have youuuuu been struggling to meet ever-tightening design schedules with more complex designs and a smaller, leaner design team?” He picks up the pace, enunciating each word with perfect clarity. “Do youuuuu find that the RTL methodology is too cummmmmbersome for today’s more sophisticated FPGA designs?” He widens his eyes as he meets the gazes of each member of the audience, conveying an ominous fear. “Are youuuuuuu suffering the pain and ravages of MOORE’s LAW?!?”
The crowd gasps.
“Welllllll, ladies and gentlemen, move in closer because I’m gonna tell you how to cut those design schedules. I’m gonna tell you how to Taaaaame that complexity. I’m gonna give you the secrets that will save you from the pain and agony and suffering of MOORE’s LAW!” He leans down then softens his voice again “That’s right, I’m talking about E – S – L. That’s Electronic Sysssssstem Level design ladies and gentlemen. ESL will give you back the power. ESL will give you back the control. ESL will free you from the bonds of register-transfer level design and open up NEW LEVELS of ABSTRACTION for your design team!”
He points to an average-looking engineer, strategically planted in the middle of the crowd. “You, sir! Did you or did you not describe your Four Million Gate FPGA design using only TWELVE LINES of high-level code?”
The man replies sheepishly “Why yes, I did.”
“Tell us, then, sir! Tell these good people how you cut your design schedules. Tell these good people how you freed yourself from the chains and bonds of register transfer level design. Explain to these fine folks how you used the methodology of the future – E, S, L – Electronic Sysssssstem Level Design… to elevate your design to a new level of abstraction and beat your competitors to market by months!”
If this sounds like a scene from a suite presentation at the upcoming Design Automation Conference – the Greatest Design Automation Conference on Earth, you’re probably right. ESL is rapidly earning the title of “most over-hyped technology” in design automation history. With PowerPoint presentations that would make PT Barnum proud, EDA companies are pushing everything from transaction-level simulators to block-based design entry to high-level synthesis technology by slapping the “ESL” label on it and making outlandish claims about productivity improvements and time-to-market advantages.
Even after putting these tools and technology through our anti-hype filter, however, we are left with some compelling and intriguing arguments, particularly for FPGA designers. As we’ve said before, one of the biggest reasons people choose FPGAs as an implementation platform is time to market. Because FPGAs eliminate mask costs, NRE, and fab waiting times, design iterations can be completed much more rapidly than in competitive methodologies like ASIC.
In ASIC design, verification is the long pole in the circus tent, dwarfing design and mitigating the move to ESL with something akin to Amdahl’s Law for design – taking the design phase of an ASIC down to zero still leaves you with a lengthy and expensive development cycle. In FPGA design, however, ESL has the potential to shine. Mate ESL’s rapid time to market philosophy with FPGA’s low overhead design process, and you’ve got a combination that has the potential to push out extremely complex working silicon in nothing flat.
ESL is a term that originates from the hardware design domain. However, by the name alone it is apparent that ESL incorporates facets of designing both the hardware and software that make up modern systems. On the true “system” level, ESL tools allow us to model our systems in a virtual prototype using abstract, high-level languages that don’t distinguish between what functionality is implemented in hardware or software. These models can be simulated to give a clear view of how a system will function overall – where we will find bottlenecks and what is required from the communications channels between various major components of our system.
One level below system-level modeling are ESL tools that facilitate partitioning of hardware and software. These tools typically allow an analysis of performance bottlenecks, simulation of interactions between hardware and software, and sometimes even ease the task of moving algorithms from software to hardware for acceleration. Although most software developers have never heard the term “ESL,” there will be an increasing encroachment of the technology into their space.
Once we have part of the system design earmarked as hardware, we move to the lowest level tools that are still frequently “ESL” branded – high-level hardware synthesis. Unlike conventional logic synthesis tools, high-level synthesis tools typically begin with a more abstract description of the algorithm (with either minimal timing information or no timing information at all) and synthesize down to logic gates or to an intermediate RTL description that can be processed using conventional tools.
Running parallel to all these levels of ESL abstraction are graphical design and analysis tools that allow viewing, block level description, and control of the whole tool flow. Sometimes referred to as “cockpits,” these tools also often try to squeak in under the ESL heading.
The headliner on the ESL marquis is productivity. “The design methodology for the next ten to fifteen years needs to offer us a 10-100X productivity improvement,” says Shawn McCloud, Mentor Graphics Product Line Director for High Level Synthesis. “RTL tools have been stretched by IP and re-use, but that doesn’t offer enough productivity advantage to give us ‘the’ solution. FPGAs are also a key component of ESL, whether they’re used as the final implementation technology or as a prototyping and verification vehicle.”
Mentor has been a player in the ESL market since the beginning, offering virtual prototyping software, hardware/software co-verification, high-level synthesis, and ESL design cockpit environments. Mentor is also the only major EDA supplier to have a significant presence both on the ASIC/SoC and FPGA-based design fronts. Their ESL product lines go back more than a decade, before the gurus of terminology had sifted through contenders like “ESDA,” ESLD,” and a host of others to settle on “ESL” as the industry-standard misnomer.
Probably the most experienced company delivering ESL capabilities specifically for FPGAs is Celoxica. You won’t find much snake oil originating from this company, which claims to be the world’s first public corporation specializing in ESL design tools. What you will find are complete design solutions, including everything from development tools through prototyping boards aimed at specific application domains such as high-performance video and image processing. The company provides tools that operate both on their proprietary Handel C as well as SystemC, which is somewhat of a standard for high-level modeling in ASIC design.
Adveda provides an interactive development environment (IDE) for hardware/software debugging that allows co-simulation and profiling of systems modeled in various hardware description languages (HDLs) and CPU instruction sets. Aldec supplies tools for high-level simulation and debugging of HDLs.
Bluespec does ESL synthesis from SystemVerilog, generating synthesizable Verilog RTL as output. They also provide a simulator that performs cycle-accurate simulation of the high-level design. Bluespec differentiates themselves by focusing on control generation for designs with complex datapaths and control logic.
Impulse Accelerated Technologies focuses on low-cost solutions for accelerating software algorithms into FPGA hardware. Their compilers take C source code and generate hardware accelerator modules that can be synthesized and implemented in FPGAs alongside conventional processors or alongside soft-core processors like Altera’s Nios and Xilinx’s MicroBlaze that are implemented in the FPGA fabric itself.
CriticalBlue’s Cascade automatically synthesizes a programmable coprocessor from a software executable. Unlike other solutions that synthesize high-level language to hardware, Cascade works from the executable binary and produces an optimized processor for the instructions used in that application. By optimizing memory and bus communications for each application, they are able to produce a more efficient, faster, lower-power alternative to offload the primary processor. This is particularly potentially valuable when using lower performance processors such as the soft-core embedded processors available for modern FPGAs.
Poseidon’s Triton environment covers the gamut from system-level simulation using SystemC to the identification and eradication of performance bottlenecks caused by inefficient hardware/software partitioning. Their Triton Builder generates co-processors to accelerate performance-intensive portions of your algorithm, offloading your primary processor. Poseidon’s solutions target both FPGA and ASIC design methodology where complex systems-on-chip (SoCs) are being designed with both custom hardware and software components.
Teja technologies focuses on the networking and communications markets with their solutions that facilitate multi-core implementations of networking applications on FPGAs. Beginning with ANSI C, Teja’s tools partition your packet processing algorithm into a pre-designed multi-processor fabric with additional IP elements for communications and algorithm acceleration.
Not wanting to miss out on the party, both Xilinx and Altera have recently announced ESL initiatives of their own, partnering with a number of suppliers of ESL tools to assure that the handoff from ESL to FPGA is as seamless as possible and to try to capture the productivity advantages of ESL design for their own customers. Each company made announcements at about the time of the Embedded Systems Conference in the spring.
Xilinx says they are partnering with a number of companies including Bluespec, Celoxica, CriticalBlue, Impulse Accelerated Technologies, Mitrionics, Nallatech, Poseidon Design Systems, SystemCrafter, and Teja Technologies. Altera says they work with Adveda, Aldec, Bluespec, Cadence, Celoxica, Impulse Accelerated Technologies, Mentor Graphics, Summit, SynaptiCAD, Synopsys and Synplicity. Tools covered by these partnerships for both FPGA vendors run the entire gamut of ESL, including high-level modeling and simulation, hardware/software partitioning and co-simulation, high-level synthesis, and partitioning of complex designs across multiple FPGA devices.
Altera has also recently announced their own C-to-hardware compiler, designed to work with their Nios II soft-core processor to generate hardware accelerators. Altera’s tool is intended to facilitate software/hardware co-design in Altera FPGAs by blurring the line between parts of an algorithm that must be executed in software on an embedded processor and what can be accelerated in hardware using resources like embedded hardware multiply-accumulate (MAC) units.
The constellation of companies involved in ESL is expanding almost every day. Between fast-moving startups and forward-thinking stalwarts, the design automation industry is rallying beneath the ESL banner. Like any technology trend, however, there are equal parts fact and fad, and it pays to be wary of marketing claims that sound too good to be true. Remember, there’s an engineer born every minute…