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Design Challenges Flow Downstream

Innovations within one domain of electronic product design typically have an unforeseen impact on other areas. For instance, innovation within FPGA devices that has enabled increased functional complexity and I/O performance has introduced challenges downstream during PCB design. Increased functional complexity has resulted in increased I/O pins per device and increased package pin density. In addition, increased I/O performance has resulted in a tighter set of PCB interconnect constraints to minimize degradation of high-speed signals as they travel between devices. The ability to leverage FPGA I/O flexibility to optimize FPGA/PCB performance offers significant value, but has been well documented, and will not be addressed in this article.

Impact of increased functional complexity

The drive towards complex systems-on-FPGA has coupled with the drive for reduced product form factors, resulting in the perfect storm on a PCB: incredibly high pin count devices packed into incredibly small packages. The PCB designer has been left with the challenge of effectively connecting the high-density device to the rest of the components on the board. Decreasing the dimensions (e.g. trace widths/spacings and drill hole sizes) of traditional copper-on-laminate through-hole PCB structures so the connections can be made has not worked – the reduced dimensions stretched the PCB fabrication envelope, resulting in lower than acceptable yields.

High-density interconnect

HDI technology has evolved from silicon fabrication processes. When coupled with traditional PCB laminate structures, interconnect densities on-board can be increased significantly, enabling connection to high-pin-density devices without sacrificing yield. The need for HDI occurs around 100 pins per square inch (another qualifier is 0.8mm pin pitch or below). At this point, traditional PCB traces with through-hole vias cannot fit into the allotted space under the component. The alternative is to consume more area for device fan-out (escape paths) outside the device or consume additional signal layers (at significant cost).

Although the technology would seem to be prohibitively expensive, it can actually lower costs due to a reduction in (traditional PCB) laminate layers and smaller boards (i.e. more boards per panel). Its smaller dimensions also result in improved electrical, thermal and electromagnetic performance.


Figure 1: HDI interconnect layers utilizing microvias on top of conventional laminate structure with through-hole vias.

Embedded passives

To facilitate increased on-chip functionality, additional passive devices (e.g. terminating resistors and decoupling capacitors) are required. By some estimates, passive components constitute 70-80% of the total part count, and this percentage continues to grow as passive-to-active ratios grow. While the active components are being packaged into larger ball grid arrays (BGAs), the ideal surface placement space for discrete passive components becomes more difficult to obtain. Currently, using surface mount device ( SMD) passives mounted on the top and bottom of a PCB takes up a lot of space and since some discretes must be placed away from the FPGA they serve, this can have a negative effect on system performance. By embedding these passives on the inner layers of the PCB, designers can significantly reduce the size of the PCB and optimize performance.

Addressing the challenges of embedded passives leads to some important benefits (besides size). Using embedded passive components allows for higher frequency (faster) PCBs. The linearity of signals through embedded integral passive components reduces inductance of “core to surface, return to core” signal paths. Along with lower inductance, embedded integral passive components can lower power system impedance and radiated emissions – improving the overall electrical performance of a PCB.

Using embedded components can also lead to reduced system costs. This includes the overall system costs that are reduced by eliminating SMDs (components, assembly) and board area. In addition, more boards per panel can be obtained, a smaller bill of materials (BOM) is necessary and there is less rework time and cost.


Figure 2: Conventional PCB with discrete SMD passive components (top) and
embedded passives integrated into the laminate substrate (bottom).

Note that ultra-small product form factors have also driven the need for embedded discrete active components. While additional surface space is made available for other active components, embedded discrete active components are not packaged, leading to smaller footprints for the active component.

FPGA vendors have been working on another alternative to the passive device explosion. Some FPGAs now come with terminating resistors built into the device, minimizing the need for on-board devices. Some even have built-in decoupling capacitors. The jury’s still out on whether this on-chip technology can make a significant dent in the volume of on-board passives.

Impact of increased I/O performance

High-end FPGAs leverage SERDES (serializer/deserializer) technology for multi-gigabit serial bus interconnects between devices. This technology replaces the traditional parallel bus architecture, enabling faster and cleaner data communication. While SERDES minimizes the number of traces on-board (it can use less than 25% of the typical interconnect paths between devices), it can increase the complexity of constraints on signal paths. SERDES signals travel down very tightly delay-and-impedance-matched differential pairs. This impacts signal routing, and usage/placement of terminating resistors.

There is also a significant impact on the verification of multi-gigabit signals. Special methodologies like eye diagrams are used to judge whether signal quality is sufficient for a data stream to be recovered at the receiver IC. Analysis must include advanced effects like lossy transmission lines and advanced via modeling that goes beyond the simple lumped-capacitor models that are commonly used in SI simulation tools. Device and interconnect model quality is critical to achieving accurate simulation results, and has required strong collaboration between silicon vendors and simulation tool vendors.


Figure 3: Eye diagram of a multi-gigabit signal.

Note that FPGA flexibility enables optimization of output drive strength to ensure signal propagation and minimize degradation due to ringing. Because this optimization can also minimize use of discrete terminations, the component and layer-count costs are reduced.


Today’s advanced FPGAs can add significant value to overall system function and performance, but can also introduce challenges to other areas of the system’s design such as the PCB. Awareness of these challenges and effective collaboration between FPGA and PCB designers can result in an end-product that is optimized for system performance and cost.

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