feature article
Subscribe Now

FPGA Journal Turns Two

FPGA Journal Turns Two

It’s time again to bring home that cake from the grocery store bakery, ditch the box, mess around with the frosting a bit so it looks more “homemade,” and tell the guests that you spent all afternoon baking it. FPGA Journal is turning 24 months old (that’s 11000 for those of you that absolutely can’t let go of binary math, even for a party). Since October 1, 2003, we’ve brought you hundreds of feature articles, thousands of press releases, a good number of controversies, and 104 weekly e-mail newsletters.

This week, in addition to our 2-year anniversary, we’re celebrating the launch of our new sister publication: “Embedded Technology Journal.” We think Embedded Technology is a good companion to FPGA Journal, with a little bit of overlap and a whole lot of new audience and material to cover. If your FPGA designs are part of embedded system designs (or if your embedded system designs are inside your latest FPGA), you will probably want to subscribe to that publication as well. In pre-release it broke all records with over 4,000 subscribers pre-registering for the new pub.

We also launched our completely re-vamped job site “Journal Jobs” ( www.journaljobs.com) this summer. If you haven’t seen the new site yet, go check it out. You just might find your next promotion. Since the re-work, Journal Jobs has had an 8X increase in average daily traffic and is still growing.

Finally, in case you didn’t notice, we’ve changed our name. With the increasing importance of structured ASIC technology in the market and the growing number of readers flocking to our structured ASIC articles, we decided it was time to acknowledge the coming of age of structured ASIC in our masthead. Our articles will still be the same, but now we have a sign out front to tell structured ASIC folks that it’s OK, they can come inside and feel welcome too.

FPGA Journal has continued to grow, now with over 50,000 total readers in over 90 countries, and with almost 16,000 subscribers to our weekly e-mail newsletter. We appreciate your continued interest in making us now the premier FPGA-related publication in the world. Over the past year, we’ve seen a number of interesting developments and received a considerable amount of feedback from you on what we’ve said and how we’ve said it.

Our most read (and easily most controversial) article of year number two was “World’s Best FPGA Article” which poked more than a little fun at the battle of superfluous superlatives among FPGA and EDA companies vying for your company’s consideration and cash. The article also got (by far) the most reader feedback we’ve ever received, with over 300 e-mails like:

“Kudos on your “World’s Best FPGA Article”! Having followed the FPGA market for a number of years, some time ago I came to the conclusion that it was, to steal from Disney, “The Happiest Place on Earth”, or at least the happiest semiconductor market on Earth, where every vendor can simultaneously claim to offer the industry’s fastest, most highly integrated, most capable, lowest power, cheapest devices.”


“well said! As a newcomer to the FPGA space the high silliness of the marketing posturing is very 1970s. Do these guys still wear leisure suits?”


“I laughed 31% more at your recent headliner article than any other article I’ve read.*
*In the last 6.2 weeks…”

We also got a considerable amount of feedback for “Ditchin’ DAC” – our look at the paradoxical purgatory perennially enveloping the venerable Design Automation Conference. On the plus side we got comments like:

“As one who was in charge of the [XXX] DAC “presence” for 7 shows… I read your article with lots of head nodding, smiles and murmurs of ‘so true, so true.’ While I’m sure DAC has declined further since [the] Mentor/Daisy/Valid days, the signs were already there – the race for space, the elaborate suites and lavish customer parties. We had nothing to show for it afterwards, of course, other than the fact that we had stood toe to toe with [our competitors].

But at least then EDA was drawn in much bolder, black and white lines. It was M/D/V and everyone else. No one was talking plug and play or interoperability. Hell, no one was using the word ‘cooperate’! The competition was clear cut, cut throat, no quarter given or taken. DAC wasn’t a trade show, it was a battlefield – and great fun.

I expect that fun, that smell of gunpowder, is long gone from DAC. Which makes it just another trade show. That makes it well worth ‘ditchin.’

Thanks for a great article.”

We also got some strong disagreement, like:

“First, it’s unfortunate that you think that DAC has stopped making sense.  Fortunately for this year’s 5,505 conference attendees, they see its relevance, importance and value.  Your position that the real vendor/customer ratio at DAC’s tradeshow is as high as three or four to one is inaccurate.  The number of exhibit attendees and other participants came in at 4,689, which means that DAC had 816 more conference attendees than tradeshow staff.  My math is probably not as good as yours, but my estimates put the vendor/customer ratio at less than one to one (.85 to one).
The DAC Technical Program Committee is made up of many dedicated, highly qualified and deeply technical individuals who volunteer countless hours to make the technical program an incomparable four-day forum.  From early attendee feedback and anecdotal information, they succeeded.  Did you know that the technical program had 57 regular sessions, nine special sessions and eight panels from the more than 730 submissions?  Acceptance rate is approximately 20 percent.  This suggests to me that competition is fierce and quality is exceptionally high.
In the early days of the Internet, I believed like you that trade shows and technical conferences would go the way of buggy whips.  John Cooley convinced me otherwise.  He believes that a conference such as DAC is as valuable today as in the past, if not more so for its networking opportunities.  With our reliance on technology, many of us work out of a home office and don’t network regularly.  DAC may be the only place to find individuals with common interests, allowing attendees to build relationships and develop business contacts.”

The biggest silicon story of the year is clearly the brewing battle in low-cost, high-volume FPGAs. Xilinx, Altera, Actel, Lattice Semiconductor, QuickLogic, and Atmel have all invested enormous engineering and marketing resources in launching product lines aimed at this potentially lucrative new market segment. As they’ve done so, the pressure has mounted to bring down advanced capabilities from high-end FPGA lines into the low-end product families. As a result, the capabilities on the low-cost products are increasing and the price of the high-end products is dropping like a rock. Eventually, there may be a continuous line between the two, and the result will be better for all of us as consumers.

On the tools front, the hottest trend right now is in tools that take you from algorithm to architecture – starting with “programming” languages like C, C++, and various hardware-modified dialects of the two and generating hardware architectures directly without requiring you to write a bunch of bad ol’ RTL/HDL. People are wanting to use these tools for everything from DSP design acceleration to reconfigurable computing to portable IP design, and for everybody from hard-core digital designers to never-thought-about-hardware software engineers. Compounding the confusion is the fact that Dataquest decided to throw these tools into their ill-defined and even less understood “ESL” category. It’s like a shopkeeper throwing his diamonds into a bin with glitter, rhinestones, and sequins and labeling it “sparkly trail mix”, then trying to decide how much to charge for a pound.

We also continued our series of personality profiles, with features on Mentor CEO Wally Rhines, Xilinx CEO Wim Roelandts, Altium Founder Nick Martin, QuickLogic CEO E. Thomas Hart, and Nallatech Founder Allan Cantle. These people and the companies they run have a profound impact on the electronics industry, and we’re lucky to have the chance to sit down and chat with them on their philosophies, predictions, and plans. Once again, we appreciate the time these experts spent with us to share their views on the industry, and we plan to continue this series through 2006 as well.

Altogether, year two was a fantastic success for FPGA Journal. We want to thank you, our readers, for your continued patronage and feedback. We also want to give a big thanks to our sponsors, now too numerous to list, who keep the lights on for all of us. Finally, I want to thank the dedicated people who work to bring you FPGA Journal each day including: Laura Domela – chief web designer, Kayla Kurucz – business development, Shirley Rice – copy editor, and Amy Malagamba – contributing editor.

Leave a Reply

featured blogs
Nov 27, 2023
Qualcomm Technologies' SVP, Durga Malladi, talks about the current benefits, challenges, use cases and regulations surrounding artificial intelligence and how AI will evolve in the near future....
Nov 27, 2023
Employees of our Cadence Cork team recently volunteered to be part of an exciting journey with our learners from Age Action. Age Action is Ireland's leading advocacy organization for older people and aging. The organization provides practical programs to support older pe...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines. Also join us for a webinar on the future of the Programmable Solution Group.

Register now: intel.com/leap

featured chalk talk

Intel AI Update
Sponsored by Mouser Electronics and Intel
In this episode of Chalk Talk, Amelia Dalton and Peter Tea from Intel explore how Intel is making AI implementation easier than ever before. They examine the typical workflows involved in artificial intelligence designs, the benefits that Intel’s scalable Xeon processor brings to AI projects, and how you can take advantage of the Intel AI ecosystem to further innovation in your next design.
Oct 6, 2023