There’s something of a Renaissance going on at Lattice semiconductor right now. Since forming their partnership with Fujitsu about a year ago, the company has sustained a steady stream of relevant announcements of new, competitive product lines. Not content to stay put in the commodity CPLD business, Lattice is mounting an aggressive campaign to capture a share of the emerging value-based FPGA market.
This week, Lattice stepped up their attack with the announcement of their new Lattice-XP line. Continuing the recent “Wolf in Sheep’s Clothing” trend in flash-based programmable logic, this family is a hybrid technology, seeking the benefits of non-volatile flash technology combined with the usual advantages of SRAM-based FPGAs. Lattice accomplishes this blend by adding on-chip flash RAM, which is capable of configuring the SRAM-based LUT architecture (the same as in their new EC and ECP lines). This makes Lattice-XP a single-chip, non-volatile FPGA with all the benefits and performance of an SRAM-based technology.
While Lattice’s EC and ECP lines seem poised to directly compete with Xilinx’s Spartan-3 and Altera’s Cyclone II, XP aims more at Actel’s recently announced ProASIC 3 line. With four aggressive companies investing heavily in the low-cost, high-volume, value-based FPGA market, the winner will definitely be the consumer. Lattice’s announcement heats up the competition and states once again that the rules and conventions of the previous FPGA market do not apply in this new space. For years, FPGA companies have competed along the same basic battle lines, derived from the needs of the telecom and networking industries. Raw performance, capacity, and reprogrammability were at a premium. Cost, power, and security were back-seat concerns.
In the value-based market, however, there are new customers with new concerns. Speed and capacity are passé. While value-based design teams still need to meet their timing specs, they care much more deeply about squeezing out the last pennies of total system cost, protecting their products from reverse-engineering, cloning, and overbuilding, reducing the board area required, and keeping the power consumption under control. These customers are also unlikely to be impressed with any vendor’s track record in the old FPGA market, so we’re really looking at a fresh start on a new game.
Lattice’s new XP line brings a compelling set of capabilities to this new competition. Leveraging their EC architecture, they start with a highly cost optimized SRAM-FPGA platform, adding the flash configuration circuitry to make a self-contained, single-chip solution for high-volume applications. What does the non-volatility buy us? For starters, it eliminates the external configuration circuitry usually required for SRAM FPGAs. While the cost of a boot PROM may be insignificant in a system using a several-hundred-dollar high-end FPGA, it is a significant percentage of the cost of these new value-based FPGA solutions. By eliminating the need for external configuration, you can chop off as much as three dollars from the BOM, plus save on board real estate and design complexity.
With the large volume of manufacturing moving to uncontrolled environments, security is an increasing concern, even for manufacturers of consumer-level products. In the field, the single-chip solution is more secure, providing a major obstacle for evildoers trying to clone, overbuild or reverse-engineer your latest design. The onboard configuration cannot be dumped, so the usual security vulnerability between configuration ROM and FPGA is eliminated.
Lattice’s XP family also provides a very fast startup time, bypassing the tens to hundreds of milliseconds usually required to get an SRAM device configured and ready. XP can be ready to rock-and-roll in about one millisecond, making it a viable solution for power-up control logic and reset-related tasks. The fast cycle time also makes it practical to power down the device for standby operation without taking a major time- or power-hit to reconfigure the device and bring it back online.
If you’re worried about neutron-induced single-event upsets (SEUs) in high reliability or high altitude applications, XP’s flash-based configuration storage allows regular cycling of the configuration of the device to mitigate the impact of any SEUs affecting the configuration logic. Lattice’s solution provides a midpoint between the almost total immunity of Actel’s pure flash-based architecture and other vendors’ more vulnerable pure SRAM-based architectures. SEU-related errors are very rare, however, usually estimated in the range of one event in hundreds of years of operation at ground level. Most of the concerns with this issue are in designs that are in space or at high altitude, or in ground-based systems that must operate reliably with a large number of FPGAs for a long period of time between power cycles.
Now that FPGAs have made significant inroads into the production-volume arena, designers are starting to realize that there is more to consider than the classic FPGA versus ASIC tradeoff between NRE and unit cost. FPGAs, it turns out, offer significant benefits in the end product because of reprogrammability. (Who would have guessed?) More often these days, FPGAs are chosen because design teams have found that reprogrammability can be leveraged in novel ways to increase functionality, improve flexibility, and lengthen the lifecycle of a product in the field.
With reprogrammability becoming a focus, LatticeXP offers a helpful twist that increases design options. While the device is operating from an active configuration in the SRAM cells, a new configuration can be loaded into the flash RAM. Then, the device can be almost instantly reconfigured with the new configuration. For designs that have a “startup” mode and an “operation” mode, this can be a helpful aid, and can effectively increase the logic capacity of the FPGA. It also opens the door for a wide variety of clever applications that Lattice probably never envisioned when they created the architecture.
By the numbers, LatticeXP will range from the XP3 device (3.1K LUTs) to the XP20 device (19.7K LUTs). (Kudos to Lattice for not trying to confuse us with estimates of system gates or ASIC-equivalent gates.) The devices also include both block and distributed RAM ranging from 54Kbits block and 12Kbits distributed on the XP3 to 414Kbits block and 79Kbits distributed on the XP20. Part of the magic of Lattice’s architecture (common to the EC/ECP families as well) is the balance of logic cells that do and do not support distributed RAM. Realizing that only a small fraction of cells are actually needed for distributed RAM in any given design, Lattice saves considerable space (and power) by only building distributed RAM capability into 25% of the logic cells. This gives enough distributed RAM where you want it, without the overhead on the majority of logic cells.
Two versions of each device are available, one with a legacy-compatible 3.3V, 2.5V or 1.8V supply, and one with a miserly 1.2V supply. This allows design teams to capitalize on the efficiency of 1.2V design for newer designs, but still maintain compatibility with existing boards and power supplies for re-spins of existing products. By providing these capabilities in separate versions of each device, Lattice is able to further increase the cost savings.
Performance-wise, Lattice joins the “fast enough” club in the value-based segment with support for designs in excess of 225MHz. Market research is rampant in this segment, trying to identify the magic clock frequency that will capture the lion’s share of the value-based market without adding to device cost. For some vendors, there is also the concern of cannibalizing high-end FPGA families with low-cost offerings that are too fast. Lattice’s 225MHz claim should be enough to satisfy most (if not all) of their target market.
Continuing their renegade trend of announcing close to actual product availability, Lattice says that the middle-of-the-range XP10 is sampling now, and is expected to be available in production volume in Q2 this year. The remainder of the family members are also expected to come online during the first half of 2005. Also breaking the industry trend, Lattice is announcing published pricing at $32.95 for immediate shipment in volumes of 1K, and projected prices of less than $15 for XP10 at 250K volume.
Given the prolific performance of Lattice’s engineering over the past months, we’d speculate that the announcements aren’t done yet. This, combined with the announcements of other FPGA vendors in recent weeks, makes it clear that every major player in the market sees huge potential in the value-based segment and is willing to fight to capture their share. While it’s far too early to predict a winner, it is clear that this game won’t be played by the usual rules of programmable logic and won’t be won with the usual tactics of FPGA marketing and technology. We expect to see a steady stream of innovative products like LatticeXP that will drive an increasing migration of high-volume electronics products toward programmable solutions.