feature article
Subscribe Now

Making the Jump to 10G

There is a radical shift in the beliefs about high speed serial feasibility as it moves beyond 3 Gbps on up to 10 Gbps. In a matter of few short years, the industry has gone from saying “impossible” to the concept of 10 Gbps with existing CMOS NRZ signaling to today, where all the required productized elements are in place for delivering manufacturable systems operational anywhere from 2.5 to 10Gbps. These components include: off the shelf transceivers, backplanes and connectors.  The reason for this shift has been a concerted, partnered effort by all parties including semiconductor vendors, backplane, connector manufacturers and signal integrity experts. Moving beyond 3 Gbps was not going to happen just by having super connectors or ultra high speed silicon or exotic materials. A strong coalition between all the players mentioned above has moved the entire industry forward.

Xilinx has not only found itself in the middle of this transition, but also played an integral role in it. Central to emergence of key technologies such as high speed transceivers, standardized backplanes and connectors has been the availability of advanced, high performance 2.5 to 10Gbps transceivers integrated into a highly digital, programmable environment such as the Xilinx Virtex™-II Pro X/ Virtex-4 FPGAs. With the wide availability of such devices, high speed serial is now available to every digital designer building systems today. FPGAs with serial I/O have created a tipping point for serial I/O. No longer is high speed serial the domain of a few who could afford to develop custom chips, backplanes and connectors in order to achieve their performance targets.

Looking back at the path traversed to get to where we are today, from the year 2000 where bold predictions about optical 10G backplanes were made, to the year 2003, the industry was attacking the problem by seeking to independently improve each of the individual elements. Gradually, as engineers started working on solving the challenges, they initially focused on high performance backplanes with exotic materials and connectors. As soon as these components were manufactured, designers realized that connectors and materials are not always the limiting factors and good design practices can actually enable the use of mainstream materials and connectors. Once this became clear, the cost associated with building 10G became less of a factor. As a result, most of the mechanical layer elements and capability for building 10G systems are in place today.

The other inflection point in this scenario was the availability of high speed transceivers capable of driving 10G signaling. Only a few such devices were available, most likely custom, and based on technologies other than CMOS. Multi-level signaling techniques other than standard NRZ were also being proposed. But substantial investments in evaluating the actual potential of multilevel signaling showed that, in fact, it could not actually deliver the imagined performance. Additionally, using such devices was extremely cost prohibitive to build 10G systems, and further presented interoperability issues. In the meantime, 10G transceivers emerged based on a standard CMOS process using NRZ signaling in an off-the-shelf part such as the Virtex-II Pro X FPGA. This provided the strong and timely boost needed to cross this barrier as well. All of the conceptual 10G systems now became reality as Xilinx, working in concert with other manufacturers, demonstrated Virtex-II Pro X driving 10 Gbps across all major backplanes and connectors over the last year.

As a result, from the end of last year, most major backplane and connector vendors either have announced or will be announcing backplane and connector products that can be manufactured today. Historically, in any industry, once standardization occurs around any standard or milestone, the cost of building products or systems around that standard nosedives. This is for 10G systems as well – as the costs have gone down with the availability of standardized components, the industry is now poised to make the jump to 10G with ease.


Leave a Reply

featured blogs
Sep 21, 2021
Placing component leads accurately as per the datasheet is an important task while creating a package footprint symbol. As the pin pitch goes down, the size and location of the component lead play a... [[ Click on the title to access the full blog on the Cadence Community si...
Sep 21, 2021
Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging. The post High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1 appeared first on From Silicon To Softw...
Sep 18, 2021
Projects with a steampunk look-and-feel incorporate retro-futuristic technology and aesthetics inspired by 19th-century industrial steam-powered machinery....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Accurate Full-System Thermal 3D Analysis

Sponsored by Cadence Design Systems

Designing electronics for the data center challenges designers to minimize and dissipate heat. Electrothermal co-simulation requires system components to be accurately modeled and analyzed. Learn about a true 3D solution that offers full system scalability with 3D analysis accuracy for the entire chip, package, board, and enclosure.

Click here for more information about Celsius Thermal Solver

featured paper

An Engineer's Guide to Designing with Precision Amplifiers

Sponsored by Texas Instruments

This e-book contains years of circuit design recommendations and insights from Texas Instruments industry experts and covers many common topics and questions you may encounter while designing with precision amplifiers.

Click to read more

featured chalk talk

In-Chip Sensing and PVT Monitoring

Sponsored by Synopsys

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Click here for more information about in-chip monitoring and sensing