Two ongoing questions have plagued analog design for many years:
- How can we design analog circuits more quickly and more portably?
- How can we keep up with the growth in circuit size while still providing gold-standard sign-off simulation in a “reasonable” time? The meaning of “reasonable” being somewhat fluid…
At this summer’s DAC, I had a couple of conversations, each dealing with one of these questions. No Holy Grails have been … Read More → "Analog Advancements"