industry news
Subscribe Now

Accellera Chair Shishpal Rawat Talks about Roadmap for IP and System Design Standards at IP-SOC 2011

Who

Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, invites IP-SOC 2011 attendees to hear Accellera chair Shishpal Rawat’s invited talk on The Roadmap for IP and System Design Standards.

What

The Roadmap for IP and System Design Standards
Shishpal Rawat, Accellera Chair
System, software and semiconductor design activities are converging to meet the increasing challenges of creating SoCs. Accellera is working with OSCI and the SystemC working groups, as well as the IEEE and other standard bodies, to facilitate the creation of system design and IP standards that reduce the cost of electronic design and increase productivity. This presentation will cover our groups’ standard activities — IP Tagging, IP-XACT™, Open Verification Library (OVL), Standard Co-Emulation Modeling Interface (SCE-MI), Unified Coverage Interoperability Standard (UCIS) and Universal Verification Methodology (UVM™) — the benefits of our standards, their fit with SystemC, and the roadmap for adoption.

When/Where

17:15 – 18:45, Wednesday, 7 December, 2011
World Trade Center
5 place Robert Schuman
38 000 Grenoble
France

Information and Registration

To register for IP-SOC, please visit http://www.design-reuse.com/ipsoc2011/registration/.

For more information about Accellera, please visit www.accellera.org.

About IP-SOC

IP-SOC is the leading industry event for the Intellectual Property (IP) and Embedded Electronic Systems community.

About Accellera

Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera’s partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

For membership information, please email membership@accellera.org.

Leave a Reply

featured blogs
Apr 19, 2024
In today's rapidly evolving digital landscape, staying at the cutting edge is crucial to success. For MaxLinear, bridging the gap between firmware and hardware development has been pivotal. All of the company's products solve critical communication and high-frequency analysis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Gas Monitoring and Metering with Sensirion SFC6000/SFM6000 Solutions
Sponsored by Mouser Electronics and Sensirion
In this episode of Chalk Talk, Amelia Dalton and Negar Rafiee Dolatabadi from Sensirion explore the benefits of Sensirion’s SFM6000 Flow Meter and SFC Flow Controller. They examine how these solutions can be used in a variety of applications and how you can get started using these technologies for your next design.
Jan 17, 2024
13,411 views