Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, invites IP-SOC 2011 attendees to hear Accellera chair Shishpal Rawat’s invited talk on The Roadmap for IP and System Design Standards.
The Roadmap for IP and System Design Standards
Shishpal Rawat, Accellera Chair
System, software and semiconductor design activities are converging to meet the increasing challenges of creating SoCs. Accellera is working with OSCI and the SystemC working groups, as well as the IEEE and other standard bodies, to facilitate the creation of system design and IP standards that reduce the cost of electronic design and increase productivity. This presentation will cover our groups’ standard activities — IP Tagging, IP-XACT™, Open Verification Library (OVL), Standard Co-Emulation Modeling Interface (SCE-MI), Unified Coverage Interoperability Standard (UCIS) and Universal Verification Methodology (UVM™) — the benefits of our standards, their fit with SystemC, and the roadmap for adoption.
17:15 – 18:45, Wednesday, 7 December, 2011
World Trade Center
5 place Robert Schuman
38 000 Grenoble
Information and Registration
To register for IP-SOC, please visit http://www.design-reuse.com/ipsoc2011/registration/.
For more information about Accellera, please visit www.accellera.org.
IP-SOC is the leading industry event for the Intellectual Property (IP) and Embedded Electronic Systems community.
Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera’s partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.
For membership information, please email email@example.com.