industry news
Subscribe Now

Accellera Chair Shishpal Rawat Talks about Roadmap for IP and System Design Standards at IP-SOC 2011

Who

Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, invites IP-SOC 2011 attendees to hear Accellera chair Shishpal Rawat’s invited talk on The Roadmap for IP and System Design Standards.

What

The Roadmap for IP and System Design Standards
Shishpal Rawat, Accellera Chair
System, software and semiconductor design activities are converging to meet the increasing challenges of creating SoCs. Accellera is working with OSCI and the SystemC working groups, as well as the IEEE and other standard bodies, to facilitate the creation of system design and IP standards that reduce the cost of electronic design and increase productivity. This presentation will cover our groups’ standard activities — IP Tagging, IP-XACT™, Open Verification Library (OVL), Standard Co-Emulation Modeling Interface (SCE-MI), Unified Coverage Interoperability Standard (UCIS) and Universal Verification Methodology (UVM™) — the benefits of our standards, their fit with SystemC, and the roadmap for adoption.

When/Where

17:15 – 18:45, Wednesday, 7 December, 2011
World Trade Center
5 place Robert Schuman
38 000 Grenoble
France

Information and Registration

To register for IP-SOC, please visit http://www.design-reuse.com/ipsoc2011/registration/.

For more information about Accellera, please visit www.accellera.org.

About IP-SOC

IP-SOC is the leading industry event for the Intellectual Property (IP) and Embedded Electronic Systems community.

About Accellera

Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera’s partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

For membership information, please email membership@accellera.org.

Leave a Reply

featured blogs
Jul 6, 2022
With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and 1c nodes along with the DRAM device speeds going up to 8533 for Lpddr5/8800 for DDR5, Data integrity is becoming a... ...
Jul 6, 2022
Design Automation Conference (DAC) 2022 is almost here! Explore EDA and cloud design tools, autonomous systems, AI, and more with our experts in San Francisco. The post DAC 2022: A Glimpse into the World of Design Automation from the Cloud to Cryogenic Computing appeared fir...
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Synopsys USB4 PHY Silicon Correlation with Keysight ADS Simulation

Sponsored by Synopsys

This video features Synopsys USB4 PHY IP showing silicon correlation with IBIS-AMI simulation using Keysight PathWave ADS.

Learn More

featured paper

Addressing high-voltage design challenges with reliable and affordable isolation tech

Sponsored by Texas Instruments

Check out TI’s new white paper for an overview of galvanic isolation techniques, as well as how to improve isolated designs in electric vehicles, grid infrastructure, factory automation and motor drives.

Click to read more

featured chalk talk

Solutions for Heterogeneous Multicore

Sponsored by Siemens Digital Industries Software

Multicore processing is more popular than ever before but how do we take advantage of this new kind of processing? In this episode of Chalk Talk, Jeff Hancock from Siemens and Amelia Dalton investigate the challenges inherent in multicore processing, the benefits of hypervisors and multicore frameworks, and what you need to consider when choosing your next multicore processing solution.

Click here for more information about Multicore Enablement: Enabling today’s most advanced MPSoC systems