editor's blog
Subscribe Now

Costs for Sub-20nm Wafers put Another Nail in Moore’s Law’s Coffin

 

IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore’s Law. Now please take care. There’s a vertical line between the 200mm wafers on the left going down to 0.13 micron lithography and 300mm wafers on the right, going down to 20nm. Per-wafer costs more than doubled going from 0.13 microns to 90nm, but the available real estate on a 300mm wafer is more than twice that on a 200mm wafer, so the cost per square nanoacre of silicon has stayed pretty constant.

(Note that the figure is labeled “revenue” but that’s from the foundry’s perspective. To the foundry customer, it’s a cost.)

But look at the jump in per-wafer costs between 28nm and 20nm (and below). There’s a sharp cost jump of slightly more than 2x, with no increase in nanoacerage. Sure, you can get more chips per wafer thanks to shrinking feature sizes, but that’s not usually what happens. The next-generation chip always has to incorporate more features. That tall bar on the far right of the graph should be drawn as a nail because it’s going into the coffin lid for Moore’s Law, which is an economic law.

As a reminder, here are the words that Moore originally used to describe the phenomenon he was seeing back in 1965:

 

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year.”

 

Moore’s Law is not just about doubling. It’s about doubling component count at a minimum cost per component.

The latest McClean Report also says, “There will probably be only three foundries able to offer high-volume leading-edge production over the next five years.” Which three? TSMC, Samsung, and Intel. The cost of joining this club is so high, it’s a safe bet that no other company is going to apply. In fact, Globalfoundries just cancelled its club membership because the dues were becoming too high. (See “Monty Python, Dead Parrots, Moore’s Law, and the ITRS.”)

 

For more information about The 2018 McClean Report from IC Insights, click here.

 

 

One thought on “Costs for Sub-20nm Wafers put Another Nail in Moore’s Law’s Coffin”

Leave a Reply

featured blogs
Jul 5, 2022
The 30th edition of SMM , the leading international maritime trade fair, is coming soon. The world of shipbuilders, naval architects, offshore experts and maritime suppliers will be gathering in... ...
Jul 5, 2022
By Editorial Team The post Q&A with Luca Amaru, Logic Synthesis Guru and DAC Under-40 Innovators Honoree appeared first on From Silicon To Software....
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Synopsys 112G Ethernet IP Interoperating with Optical Components & Equalizing E-O-E Link

Sponsored by Synopsys

This OFC 2022 demo features the Synopsys 112G Ethernet IP directly equalizing electrical-optical-electrical (E-O-E) channel and supporting retimer-free CEI-112G linear drive for low-power applications.

Learn More

featured paper

3 key considerations for your next-generation HMI design

Sponsored by Texas Instruments

Human-Machine Interface (HMI) designs are evolving. Learn about three key design considerations for next-generation HMI and find out how low-cost edge AI, power-efficient processing and advanced display capabilities are paving the way for new human-machine interfaces that are smart, easily deployable, and interactive.

Click to read more

featured chalk talk

Faster, More Predictable Path to Multi-Chiplet Design Closure

Sponsored by Cadence Design Systems

The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.

Click here for more information about Integrity 3D-IC Platform from Cadence Design Systems