editor's blog
Subscribe Now

Costs for Sub-20nm Wafers put Another Nail in Moore’s Law’s Coffin

 

IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore’s Law. Now please take care. There’s a vertical line between the 200mm wafers on the left going down to 0.13 micron lithography and 300mm wafers on the right, going down to 20nm. Per-wafer costs more than doubled going from 0.13 microns to 90nm, but the available real estate on a 300mm wafer is more than twice that on a 200mm wafer, so the cost per square nanoacre of silicon has stayed pretty constant.

(Note that the figure is labeled “revenue” but that’s from the foundry’s perspective. To the foundry customer, it’s a cost.)

But look at the jump in per-wafer costs between 28nm and 20nm (and below). There’s a sharp cost jump of slightly more than 2x, with no increase in nanoacerage. Sure, you can get more chips per wafer thanks to shrinking feature sizes, but that’s not usually what happens. The next-generation chip always has to incorporate more features. That tall bar on the far right of the graph should be drawn as a nail because it’s going into the coffin lid for Moore’s Law, which is an economic law.

As a reminder, here are the words that Moore originally used to describe the phenomenon he was seeing back in 1965:

 

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year.”

 

Moore’s Law is not just about doubling. It’s about doubling component count at a minimum cost per component.

The latest McClean Report also says, “There will probably be only three foundries able to offer high-volume leading-edge production over the next five years.” Which three? TSMC, Samsung, and Intel. The cost of joining this club is so high, it’s a safe bet that no other company is going to apply. In fact, Globalfoundries just cancelled its club membership because the dues were becoming too high. (See “Monty Python, Dead Parrots, Moore’s Law, and the ITRS.”)

 

For more information about The 2018 McClean Report from IC Insights, click here.

 

 

One thought on “Costs for Sub-20nm Wafers put Another Nail in Moore’s Law’s Coffin”

Leave a Reply

featured blogs
Apr 11, 2021
https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic Duo 2: The Sequel Tuesday: Gall's Law and Big Ball of Mud Wednesday: Benedict Evans on Tech in 2021... [[ Click on the title to access the full blog on the Cadence Community sit...
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...
Apr 7, 2021
We explore how EDA tools enable hyper-convergent IC designs, supporting the PPA and yield targets required by advanced 3DICs and SoCs used in AI and HPC. The post Why Hyper-Convergent Chip Designs Call for a New Approach to Circuit Simulation appeared first on From Silicon T...
Apr 5, 2021
Back in November 2019, just a few short months before we all began an enforced… The post Collaboration and innovation thrive on diversity appeared first on Design with Calibre....

featured video

Learn the basics of Hall Effect sensors

Sponsored by Texas Instruments

This video introduces Hall Effect, permanent magnets and various magnetic properties. It'll walk through the benefits of Hall Effect sensors, how Hall ICs compare to discrete Hall elements and the different types of Hall Effect sensors.

Click here for more information

featured paper

Understanding the Foundations of Quiescent Current in Linear Power Systems

Sponsored by Texas Instruments

Minimizing power consumption is an important design consideration, especially in battery-powered systems that utilize linear regulators or low-dropout regulators (LDOs). Read this new whitepaper to learn the fundamentals of IQ in linear-power systems, how to predict behavior in dropout conditions, and maintain minimal disturbance during the load transient response.

Click here to download the whitepaper

Featured Chalk Talk

Innovative Hybrid Crowbar Protection for AC Power Lines

Sponsored by Mouser Electronics and Littelfuse

Providing robust AC line protection is a tough engineering challenge. Lightning and other unexpected events can wreak havoc with even the best-engineered power supplies. In this episode of Chalk Talk, Amelia Dalton chats with Pete Pytlik of Littelfuse about innovative SIDACtor semiconductor hybrid crowbar protection for AC power lines, that combine the best of TVS and MOV technologies to deliver superior low clamping voltage for power lines.

More information about Littelfuse SIDACtor + MOV AC Line Protection