editor's blog
Subscribe Now

Xilinx’s CEO Victor Peng Speaks About 7nm Everest/ACAP, Death of Moore’s Law. His Hot Chips 30 Keynote Now Online

Earlier this week, I published a detailed account of the HW/SW Programmable Engine that was the final, undisclosed block in the Xilinx Everest Architecture, to appear first in the company’s 7nm ACAP (the Adaptable Computing Acceleration Platform), which will tape out later this year. (See “Xilinx Puts a Feather in its ACAP: Final block in Xilinx’s 7nm Everest Architecture is Detailed at Hot Chips 30 in Cupertino.”) That article was largely based on a technical presentation given at Hot Chips 30 by Juanjo Noguera, the engineering director of the Xilinx Architecture Group.

However, Xilinx CEO Victor Peng also spoke at Hot Chips 30. In fact, he delivered an hour-long keynote speech during which he discussed the Everest/ACAP project as well as other topics that set the stage for this product’s development, including the death of Moore’s Law.

The Hot Chips 30 organizers just published an hour-long video clip of Peng’s keynote as well as the Q&A session that followed. But you’ll need to jump to YouTube to see it, or you can just watch it below.

 

Leave a Reply

featured blogs
Jan 17, 2020
I once met Steve Wozniak, or he once met me (it's hard to remember the nitty-gritty details)....
Jan 17, 2020
[From the last episode: We saw how virtual memory helps resolve the differences between where a compiler thinks things will go in memory and the real memories in a real system.] We'€™ve talked a lot about memory '€“ different kinds of memory, cache memory, heap memory, vi...
Jan 16, 2020
While Samtec started as a connector company with a focus on two-piece, pin-and-socket board stacking systems, High-Speed Board Stacking connectors and High-Speed Cable Assemblies now make up a significant portion of our sales. To support development in this area, in December ...
Jan 16, 2020
Betting on Hydrogen-Powered Cars On-demand DRC within P&R cuts closure time in half for MaxLinear Functional Safety Verification For AV SoC Designs Accelerated With Advanced Tools Automating the pain out of clock domain crossing verification Mentor unpacks LVS and LVL iss...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Click here for more information about DesignWare IP for Automotive