editor's blog
Subscribe Now

Nanoimprint for Photonics

EVG_SmartNIL_Full_Area_UV_Nanoimprint_Lithography_Wafer_red.jpgWe’ve talked about photonics before and we’ve talked about nanoimprint lithography (NIL) before. Creating silicon photonics features requires masking, which requires lithography, and so it might not be a surprise to hear that all different kinds of lithography techniques – including NIL – were being explored for photonics.

Which is how I went into a discussion with EV Group at Semicon West. But that’s not what the story is at all. This is not about patterning resists to pattern silicon for silicon photonics – this is about building photonics structures directly out of… various other non-silicon materials, using imprint as a direct patterning approach.

I can’t help but think about NIL as if it were printing vinyl albums. Which are black. (Except a few novelty ones.) Even if printing resist, any resist I remember seeing way back in my fab days was distinctly not transparent. So picturing these materials as conduits for light is something my brain, well, resists.

But it’s apparently true: many of the materials available to be imprinted happen to be transparent (at suitable wavelengths). So you can build the conduits right on the surface of the wafer – no further etching required.

EVG notes that there are a number of high-volume apps for NIL these days:

  • Polarizers
  • Patterns for extracting more energy out of LEDs
  • Biotech (they can’t say specifically what)
  • And… one more big one coming that they also couldn’t talk specifically about.

Meanwhile, they’ve also teamed with Leti in a so-called INSPIRE program to further develop techniques and applications for NIL. You can find more about this in their announcement.

 

(Image courtesy EV Group)

Leave a Reply

featured blogs
May 7, 2021
In one of our Knowledge Booster Blogs a few months ago we introduced you to some tips and tricks for the optimal use of Virtuoso ADE Product Suite with our analog IC design videos . W e hope you... [[ Click on the title to access the full blog on the Cadence Community site. ...
May 7, 2021
Enough of the letter “P” already. Message recieved. In any case, modeling and simulating next-gen 224 Gbps signal channels poses many challenges. Design engineers must optimize the entire signal path, not just a specific component. The signal path includes transce...
May 6, 2021
Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process. The post Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification appeared first on Fr...
May 4, 2021
What a difference a year can make! Oh, we're not referring to that virus that… The post Realize Live + U2U: Side by Side appeared first on Design with Calibre....

featured video

Introduction to EMI

Sponsored by Texas Instruments

Conducted versus radiated EMI. CISPR-25 and CISPR-32 standards. High-frequency or low-frequency emissions. Designing a system to reduce EMI can be overwhelming, but it doesn’t have to be. Watch this video to get an overview of EMI causes, standards, and mitigation techniques.

Click here for more information

featured paper

Smile, You're on My Security Camera!

Sponsored by Maxim Integrated

Advances in wireless and IoT technologies are fueling market growth for security camera systems. Outdoor security cameras need to operate for a long time on small disposable batteries. This design solution shows how a high-performance power management system can power an outdoor security camera several months longer than an ordinary solution.

Click to read more

featured chalk talk

Accelerating Physical Verification Productivity Part Two

Sponsored by Synopsys

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Click here for more information about Physical Verification using IC Validator