editor's blog
Subscribe Now

Cadence Refreshes Synthesis and Formal

Cadence has announced a couple of major upgrades over the last month or two. They’re largely unrelated to each other – one is synthesis, the other formal verification – so we’ll take them one at a time.

A New Genus Species

First, synthesis: they announced a new synthesis engine called Genus. Another in a recent line of new products ending in “-us.” (Upcoming motto: “One of -us! One of –us!”)

According to the Schaumburg Managed IT Services, There are a couple specific areas of focus for the new tool. But they tend to revolve around the notion that, during the day, designers work on their units; at night, the units are assembled for a block- or chip-level run.

At the chip level, physical synthesis has been possible to reduce iterations between place & route and synthesis, but unit synthesis has remained more abstract, being just a bit of logic design without a physical anchor. For both chip and unit levels, accuracy and turn-around time are important. Without physical information, unit accuracy suffers, making necessary more implementation iterations.

To address turn-around time, significant effort was placed on the ability to split up a full chip for processing on multiple computers. They use three levels of partitioning – into chunks of about 100,000 instances, then 10,000 instances, and then at the algorithm level.

Synthesis_parallelism.png

(Image courtesy Cadence)

The challenge they face in generating a massively parallel partition is that multiple machines will be needed. Within a single machine, multiple cores can share memory, but that’s not possible between machines. That means that communication between machines to keep coherent views of shared information can completely bog the process down on a poorly conceived partition.

To help with this, they partition by timing, not by physical location. So the partitions may actually physically overlap. They also try to cut only non-critical lines when determining boundaries, making less likely that multiple converging iterations will be needed.

That said, they still do several iterations of refinement, cutting and reassembling, then cutting again and reassembling. And then once more.

At the lowest level of partition, you have algorithms, and these are small enough to manage within a single machine. Which is good, because shared memory is critical here to optimize performance, power, and area (PPA).

Larger IP blocks can undergo microarchitecture optimization, where the impacts of several options are evaluated and analytically solved to pick the best PPA result.

Once an assembled chip has been synthesized with physical information, the contributing units are annotated with physical information so that subsequent unit synthesis can proceed more accurately, again, reducing overall iterations.

They’re claiming 5X better synthesis time, iterations between unit and block level cut in half, and 10-20% reduction in datapath area and power.

You can find other details about the Genus synthesis engine in their announcement.

Jasper Gets Incisive

Meanwhile, the integration of their acquired Jasper formal analysis technology is proceeding. Cadence had their own Incisive formal tools, but, with a few exceptions, those are giving way to the Jasper versions. But they’re trying to make it an easy transition.

One way they’ve done this is to maintain the Incisive front end with the new JasperGold flow. So there are two ways to get to the Jasper technology: via the Jasper front end (no change for existing Jasper users) and with the Incisive front end, making the transition faster.

Formal_picture.png

(Image courtesy Cadence)

Under the hood, they’ve kept most of the Jasper engines based on how well they work, but they also brought over a few of the Incisive engines that performed well.

We talked about the whole engine-picking concept when we covered OneSpin’s LaunchPad platform recently. In Cadence’s case, they generally try all engines and pick the best results, but they also allow on-the-fly transitions from engine to engine. This is something they initiated a couple years ago with Incisive; it now accrues to the Jasper engines as well.

They’ve also got formal-assisted simulation for deeper bug detection; they compile IP constraints first for faster bug detection (at the expense of some up front time); and they’ve provided assertion-based VIP for emulation to replace non-synthesizable checkers.

And the result of all of this is a claimed 15X improvement in performance.

You can get more detail on these and other aspects in their announcement.

Leave a Reply

featured blogs
Jul 12, 2024
I'm having olfactory flashbacks to the strangely satisfying scents found in machine shops. I love the smell of hot oil in the morning....

featured video

Larsen & Toubro Builds Data Centers with Effective Cooling Using Cadence Reality DC Design

Sponsored by Cadence Design Systems

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

Click here for more information about Cadence Multiphysics System Analysis

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured chalk talk

Ultra-low Power Fuel Gauging for Rechargeable Embedded Devices
Fuel gauging is a critical component of today’s rechargeable embedded devices. In this episode of Chalk Talk, Amelia Dalton and Robin Saltnes of Nordic Semiconductor explore the variety of benefits that Nordic Semiconductor’s nPM1300 PMIC brings to rechargeable embedded devices, the details of the fuel gauge system at the heart of this solution, and the five easy steps that you can take to implement this solution into your next embedded design.
May 8, 2024
9,895 views