editor's blog
Subscribe Now

Cadence Refreshes Synthesis and Formal

Cadence has announced a couple of major upgrades over the last month or two. They’re largely unrelated to each other – one is synthesis, the other formal verification – so we’ll take them one at a time.

A New Genus Species

First, synthesis: they announced a new synthesis engine called Genus. Another in a recent line of new products ending in “-us.” (Upcoming motto: “One of -us! One of –us!”)

According to the Schaumburg Managed IT Services, There are a couple specific areas of focus for the new tool. But they tend to revolve around the notion that, during the day, designers work on their units; at night, the units are assembled for a block- or chip-level run.

At the chip level, physical synthesis has been possible to reduce iterations between place & route and synthesis, but unit synthesis has remained more abstract, being just a bit of logic design without a physical anchor. For both chip and unit levels, accuracy and turn-around time are important. Without physical information, unit accuracy suffers, making necessary more implementation iterations.

To address turn-around time, significant effort was placed on the ability to split up a full chip for processing on multiple computers. They use three levels of partitioning – into chunks of about 100,000 instances, then 10,000 instances, and then at the algorithm level.

Synthesis_parallelism.png

(Image courtesy Cadence)

The challenge they face in generating a massively parallel partition is that multiple machines will be needed. Within a single machine, multiple cores can share memory, but that’s not possible between machines. That means that communication between machines to keep coherent views of shared information can completely bog the process down on a poorly conceived partition.

To help with this, they partition by timing, not by physical location. So the partitions may actually physically overlap. They also try to cut only non-critical lines when determining boundaries, making less likely that multiple converging iterations will be needed.

That said, they still do several iterations of refinement, cutting and reassembling, then cutting again and reassembling. And then once more.

At the lowest level of partition, you have algorithms, and these are small enough to manage within a single machine. Which is good, because shared memory is critical here to optimize performance, power, and area (PPA).

Larger IP blocks can undergo microarchitecture optimization, where the impacts of several options are evaluated and analytically solved to pick the best PPA result.

Once an assembled chip has been synthesized with physical information, the contributing units are annotated with physical information so that subsequent unit synthesis can proceed more accurately, again, reducing overall iterations.

They’re claiming 5X better synthesis time, iterations between unit and block level cut in half, and 10-20% reduction in datapath area and power.

You can find other details about the Genus synthesis engine in their announcement.

Jasper Gets Incisive

Meanwhile, the integration of their acquired Jasper formal analysis technology is proceeding. Cadence had their own Incisive formal tools, but, with a few exceptions, those are giving way to the Jasper versions. But they’re trying to make it an easy transition.

One way they’ve done this is to maintain the Incisive front end with the new JasperGold flow. So there are two ways to get to the Jasper technology: via the Jasper front end (no change for existing Jasper users) and with the Incisive front end, making the transition faster.

Formal_picture.png

(Image courtesy Cadence)

Under the hood, they’ve kept most of the Jasper engines based on how well they work, but they also brought over a few of the Incisive engines that performed well.

We talked about the whole engine-picking concept when we covered OneSpin’s LaunchPad platform recently. In Cadence’s case, they generally try all engines and pick the best results, but they also allow on-the-fly transitions from engine to engine. This is something they initiated a couple years ago with Incisive; it now accrues to the Jasper engines as well.

They’ve also got formal-assisted simulation for deeper bug detection; they compile IP constraints first for faster bug detection (at the expense of some up front time); and they’ve provided assertion-based VIP for emulation to replace non-synthesizable checkers.

And the result of all of this is a claimed 15X improvement in performance.

You can get more detail on these and other aspects in their announcement.

Leave a Reply

featured blogs
Jan 17, 2022
Today's interview features Dajana Danilovic, an application engineer based near Munich, Germany. In this video, Dajana shares about her pathway to becoming an engineer, as well as the importance of... [[ Click on the title to access the full blog on the Cadence Community sit...
Jan 13, 2022
See what's behind the boom in AI applications and explore the advanced AI chip design tools and strategies enabling AI SoCs for HPC, healthcare, and more. The post The Ins and Outs of AI Chip Design appeared first on From Silicon To Software....
Jan 12, 2022
In addition to sporting a powerful processor and supporting Bluetooth wireless communications, Seeed's XIAO BLE Sense also boasts a microphone and a 6DOF IMU....

featured video

Synopsys & Samtec: Successful 112G PAM-4 System Interoperability

Sponsored by Synopsys

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

Click here for more information about DesignWare Ethernet IP Solutions

featured paper

How to Fast-Charge Your Supercapacitor

Sponsored by Analog Devices

Supercapacitors (or ultracapacitors) are suited for short charge and discharge cycles. They require high currents for fast charge as well as a high voltage with a high number in series as shown in two usage cases: an automatic pallet shuttle and a fail-safe backup system. In these and many other cases, the fast charge is provided by a flexible, high-efficiency, high-voltage, and high-current charger based on a synchronous, step-down, supercapacitor charger controller.

Click to read more

featured chalk talk

Tackling Automotive Software Cost and Complexity

Sponsored by Mouser Electronics and NXP Semiconductors

With the sheer amount of automotive software cost and complexity today, we need a way to maximize software reuse across our process platforms. In this episode of Chalk Talk, Amelia Dalton and Daniel Balser from NXP take a closer look at the software ecosystem for NXP’s S32K3 MCU. They investigate how real-time drivers, a comprehensive safety software platform, and high performance security system will help you tackle the cost and complexity of automotive software development.

Click here for more information about NXP Semiconductors S32K3 Automotive General Purpose MCUs