editor's blog
Subscribe Now

Driving ADAS

ARM reckons that the computational power in your car is set to increase by 100X in the next ten years, mainly through the growth of ADAS (Advanced Driver Assistance Systems). These systems use sensors of many kinds to gather information about the environment, process it, and present it to the driver. While at one level all that ADAS is doing is what a reasonably alert driver does- notices speed limit signs, the position of other vehicles etc, at the next level it gets more exciting. In poor light conditions ADAS can use visual light and RADAR sensors to see better, will use image processing to decide if the dimly seen figure is a pedestrian, a cyclist or a street light and then calculate likely paths, if it is not a street light.

Just that one example will use a ton of processing power and, as the information is safety-critical, the systems to do this will have to be developed accordingly. This, in the automotive environment, means that they will need to conform to ISO 26262, which requires a mass of documentation about the components in use and the software running in the systems. Earlier this year ARM announced a package of safety documentation and support for the Cortex-R5, a core that a number of chip companies are using in processors for automotive applications.

They have now extended the programme to the Cortex-A family, with packages available for the Cortex-A53, the Cortex-A57 and the big beast of the ARM family launched earlier this year, the Cortex-A72.

SoC implementers will get help with the development and safety assessment of SoC designs to help meet the functional safety standards such as ISO 26262 and IEC 61508 through a documentation package. The package includes a safety manual, a FMEA (Failure Modes and Effects Analysis) report and a development interface report. This should shorten significantly the time and effort needed for a certification programme within an SoC company.

ARM intends to provide the same package for other processors once they have waded through the huge amount of work that providing the package involves.

Leave a Reply

featured blogs
Jan 17, 2022
Today's interview features Dajana Danilovic, an application engineer based near Munich, Germany. In this video, Dajana shares about her pathway to becoming an engineer, as well as the importance of... [[ Click on the title to access the full blog on the Cadence Community sit...
Jan 13, 2022
See what's behind the boom in AI applications and explore the advanced AI chip design tools and strategies enabling AI SoCs for HPC, healthcare, and more. The post The Ins and Outs of AI Chip Design appeared first on From Silicon To Software....
Jan 12, 2022
In addition to sporting a powerful processor and supporting Bluetooth wireless communications, Seeed's XIAO BLE Sense also boasts a microphone and a 6DOF IMU....

featured video

Synopsys & Samtec: Successful 112G PAM-4 System Interoperability

Sponsored by Synopsys

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

Click here for more information about DesignWare Ethernet IP Solutions

featured paper

Using the MAX66242 Mobile Application, the Basics

Sponsored by Analog Devices

This application note describes the basics of the near-field communication (NFC)/radio frequency identification (RFID) MAX66242EVKIT board and an application utilizing the NFC capabilities of iOS and Android® based mobile devices to exercise board functionality. It then demonstrates how the application enables the user with the ability to use the memory and secure features of the MAX66242. It also shows how to use the MAX66242 with an onboard I2C temperature sensor which demonstrates the energy harvesting feature of the device.

Click to read more

featured chalk talk

Solutions for Heterogeneous Multicore

Sponsored by Siemens Digital Industries Software

Multicore processing is more popular than ever before but how do we take advantage of this new kind of processing? In this episode of Chalk Talk, Jeff Hancock from Siemens and Amelia Dalton investigate the challenges inherent in multicore processing, the benefits of hypervisors and multicore frameworks, and what you need to consider when choosing your next multicore processing solution.

Click here for more information about Multicore Enablement: Enabling today’s most advanced MPSoC systems