editor's blog
Subscribe Now

Driving ADAS

ARM reckons that the computational power in your car is set to increase by 100X in the next ten years, mainly through the growth of ADAS (Advanced Driver Assistance Systems). These systems use sensors of many kinds to gather information about the environment, process it, and present it to the driver. While at one level all that ADAS is doing is what a reasonably alert driver does- notices speed limit signs, the position of other vehicles etc, at the next level it gets more exciting. In poor light conditions ADAS can use visual light and RADAR sensors to see better, will use image processing to decide if the dimly seen figure is a pedestrian, a cyclist or a street light and then calculate likely paths, if it is not a street light.

Just that one example will use a ton of processing power and, as the information is safety-critical, the systems to do this will have to be developed accordingly. This, in the automotive environment, means that they will need to conform to ISO 26262, which requires a mass of documentation about the components in use and the software running in the systems. Earlier this year ARM announced a package of safety documentation and support for the Cortex-R5, a core that a number of chip companies are using in processors for automotive applications.

They have now extended the programme to the Cortex-A family, with packages available for the Cortex-A53, the Cortex-A57 and the big beast of the ARM family launched earlier this year, the Cortex-A72.

SoC implementers will get help with the development and safety assessment of SoC designs to help meet the functional safety standards such as ISO 26262 and IEC 61508 through a documentation package. The package includes a safety manual, a FMEA (Failure Modes and Effects Analysis) report and a development interface report. This should shorten significantly the time and effort needed for a certification programme within an SoC company.

ARM intends to provide the same package for other processors once they have waded through the huge amount of work that providing the package involves.

Leave a Reply

featured blogs
Dec 7, 2023
Semiconductor chips must be designed faster, smaller, and smarter'”with less manual work, more automation, and faster production. The Training Webinar 'Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have' was recently hosted with me, Krishna Atreya, Princ...
Dec 6, 2023
Explore standards development and functional safety requirements with Jyotika Athavale, IEEE senior member and Senior Director of Silicon Lifecycle Management.The post Q&A With Jyotika Athavale, IEEE Champion, on Advancing Standards Development Worldwide appeared first ...
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Non-Magnetic Interconnects
Sponsored by Mouser Electronics and Samtec
Magnets and magnetic fields can cause big problems in medical, scientific, industrial, space, and quantum computing applications but using a non-magnetic connector can help solve these issues. In this episode of Chalk Talk, Amelia Dalton and John Riley from Samtec discuss the construction of non-magnetic connectors and how you could use non-magnetic connectors in your next design.
May 3, 2023
26,192 views