editor's blog
Subscribe Now

Hi Bryon, Your readers should be

Hi Bryon, Your readers should be aware that multiple customers are using Mentor Calibre in the physical verification and extraction portions of their MEMS designs. To that point, there is a white paper authored by Mentor and Freescale on how Freescale uses Calibre in their MEMS designs(http://go.mentor.com/3yxal).

When it comes to DRC, there are some unique aspects of MEMS, not the least of which is the need to accurately handle curves. This is quite different than verification of ICs, which use rectilinear shapes, or so-called Manhattan topology, and can really throw DRC tools into a tizzy, resulting in slow runtimes and potentially thousands of false violations.

Calibre nmDRC helps mitigate this problem via Calibre eqDRC, a capability that allows designers to create an equation based check that allows checking of curved designs. On the extraction side, MEMS designers like the Calibre xACT field solver extraction technology because it works directly on the physics of the design using Maxwell’s equations—that is, designers can not only get very accurate results, but they are able to get started doing extraction analysis much faster, as set up is much faster vs developing a look-up table solution.

Leave a Reply

featured blogs
Dec 7, 2023
Building on the success of previous years, the 2024 edition of the DATE (Design, Automation and Test in Europe) conference will once again include the Young People Programme. The largest electronic design automation (EDA) conference in Europe, DATE will be held on 25-27 March...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Universal Verification Methodology Coverage for Bluespec RISC-V Cores

Sponsored by Synopsys

This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and a RISC-V processor core from Bluespec.

Click to read more

featured chalk talk

Battery-free IoT devices: Enabled by Infineon’s NFC Energy-Harvesting
Sponsored by Mouser Electronics and Infineon
Energy harvesting has become more popular than ever before for a wide range of IoT devices. In this episode of Chalk Talk, Amelia Dalton chats with Stathis Zafiriadis from Infineon about the details of Infineon’s NFC energy harvesting technology and how you can get started using this technology in your next IoT design. They discuss the connectivity and sensing capabilities of Infineon’s NAC1080 and NGC1081 NFC actuation controllers and the applications that would be a great fit for these innovative solutions.
Aug 17, 2023
13,588 views