editor's blog
Subscribe Now

Universal Verification Stimulus Format

We used to be ok with the verification silos we grew up with. You’ve got your simulation guys over here helping with circuit and block verification. You’ve got your emulation group over there checking out larger system chunks or running software. In yet another corner, you’ve got your virtual platforms running software.

But really, there can be a lot of rework involved as an SoC migrates from being individual bits and pieces, individually tested, to a unified system, holistically tested. So a group at Accellera has formed to standardize a stimulus format so that verification intent and stimulus can be ported to different environments.

The scope here appears to be twofold. On the one hand, you’ve got different verification methodologies: simulation, emulation, etc. The different platforms may expect different inputs – even if just variations. On the other hand, this also appears to be about scale – blocks and components vs. complete systems.

One of the big differentiators at the system level is the use of software to test out the hardware platform. Note that this is different from using a virtual platform to test software: in that case, it’s the software that’s being tested with a “known good” platform model. The focus of this stimulus effort is more about verifying the platform itself; when software is used for that, then it’s the software that’s “known good.” So, of the silos I mentioned above, that last one seems unlikely to be affected. Then again, it’s different from the others, since it’s not about hardware verification.

Because the low-level stimulus details for, say, simulation will be different from that for software, this is more about capturing intent and verification scenarios for automated generation of the actual stimulus that makes its way into the test environment.

Drawing.png 

The first meeting just happened a week ago; if it’s an activity you’d like to be involved in, now’s a good time to jump in. Apparently a roadmap hasn’t yet been sketched out, so it’s still early days.

You can find more in their announcement.

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Maximizing Power Savings During Chip Implementation with Dynamic Refresh of Vectors

Sponsored by Synopsys

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn more about Energy-Efficient SoC Solutions

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Flexible Development with the PSoC 62S2 Evaluation Kit

Sponsored by Mouser Electronics and Mouser Electronics

In order to get a successful IoT design launched today, we need a robust toolbox of cloud connectivity solutions, sensor interfaces, radio modules, and more. In this episode of Chalk Talk, Amelia Dalton and Paul Wiegele from Infineon investigate the PSoC™ 62S2 Evaluation Kit from Infineon. They take a closer look at the key features included in this kit and how it can help jumpstart your next IoT design.

Click here for more information about Infineon Technologies PSoC® 62S2 Wi-Fi® BLUETOOTH® Pioneer Kit