editor's blog
Subscribe Now

Universal Verification Stimulus Format

We used to be ok with the verification silos we grew up with. You’ve got your simulation guys over here helping with circuit and block verification. You’ve got your emulation group over there checking out larger system chunks or running software. In yet another corner, you’ve got your virtual platforms running software.

But really, there can be a lot of rework involved as an SoC migrates from being individual bits and pieces, individually tested, to a unified system, holistically tested. So a group at Accellera has formed to standardize a stimulus format so that verification intent and stimulus can be ported to different environments.

The scope here appears to be twofold. On the one hand, you’ve got different verification methodologies: simulation, emulation, etc. The different platforms may expect different inputs – even if just variations. On the other hand, this also appears to be about scale – blocks and components vs. complete systems.

One of the big differentiators at the system level is the use of software to test out the hardware platform. Note that this is different from using a virtual platform to test software: in that case, it’s the software that’s being tested with a “known good” platform model. The focus of this stimulus effort is more about verifying the platform itself; when software is used for that, then it’s the software that’s “known good.” So, of the silos I mentioned above, that last one seems unlikely to be affected. Then again, it’s different from the others, since it’s not about hardware verification.

Because the low-level stimulus details for, say, simulation will be different from that for software, this is more about capturing intent and verification scenarios for automated generation of the actual stimulus that makes its way into the test environment.

Drawing.png 

The first meeting just happened a week ago; if it’s an activity you’d like to be involved in, now’s a good time to jump in. Apparently a roadmap hasn’t yet been sketched out, so it’s still early days.

You can find more in their announcement.

Leave a Reply

featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....

featured video

How NV5, NVIDIA, and Cadence Collaboration Optimizes Data Center Efficiency, Performance, and Reliability

Sponsored by Cadence Design Systems

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Click here for more information about Cadence Data Center Solutions

featured chalk talk

Unlock the Productivity and Efficiency of a Connected Plant
In this episode of Chalk Talk, Amelia Dalton and Patrick Casey from Schneider Electric explore the multitude of benefits that mobility brings to industrial applications. They investigate how Schneider Electric’s Harmony Hub can simplify monitoring and testing, increase operational efficiency and connectivity openness in industrial plants, and how NFC technology can bring new innovation possibilities to IIoT applications.
Apr 23, 2024
13,111 views