editor's blog
Subscribe Now

Porous Silicon and Triboelectricity

Last December’s IEDM conference included energy harvesting as a topic; a couple of papers caught my attention. You could almost think of one of them as bridging batteries and capacitors; the other leverages an everyday household phenomenon in a new way.

The first paper, from a collaboration between Intel, Florida Int’l Univ., and Univ. of Turku, demonstrated a way to create porous silicon to increase surface area in a capacitor. They do this with an etch that, in principle, is capable of a 1000:1 aspect ratio, although other limitations limited the etch depth, as we’ll see.

The idea is that, by “hollowing” out solid silicon with numerous small pores, you get the benefit of surface area inside the bulk, not just on the top of the silicon. Smaller pores mean more surface area, but they’re also harder for ions to navigate through. So they used a combination of large and small pores, tapering them slightly so that ions could more easily enter to keep the performance high.


But there’s a catch here: it turns out that, left like this, the silicon surface will oxidize and degrade after repeated cycling; the surface needs to be stabilized through a coating. They had demonstrated carbon as an effective coating, but that required high temperatures (above 650 °C). So in this work, they focused on atomic-layer deposition (ALD) of TiN. They did this at temperatures between 380 and 450 °C (and could have done 280 °C had they used a different precursor).

They used a modification of typical ALD processes, presumably because of the fact that they were depositing not on a plane, but into a porous material. The normal process is to let the precursor soak for 1-2 seconds; they gave it 30 seconds in a so-called “stop-flow” process.

While the coating stabilized the surface, it also decreased surface area. A 2.5-nm layer reduced the surface area by 13% over uncoated; a 10-nm layer reduced it by 53%. So limiting the thickness is important to maintaining performance.

As to the pore depth, they found they could etch as deep as 254 µm. But they found that, upon heating, passivating hydrogen came off – which caused stresses and cracking. This became a problem with pores deeper than 15 µm, so they limited themselves to a range of 2 – 12 µm.

This device inhabits a space between capacitors and batteries. It uses mechanisms similar to capacitors, but because it’s leveraging the hollow-out interior of the bulk, it also shares the 3D characteristics of a battery. The power is going to be determined by the mobility of the ions through the pores. But, as you can see, this competes well in power and energy densities.


And there’s another payoff: While lithium ion or lithium thin-film batteries can be cycled only a hundred or so times, the porous silicon device could be charged hundreds of thousands of times.

Meanwhile, in a totally different vein, a team from KAIST and NASA Ames experimented with “triboelectricity” – essentially, the kind of static electricity you build up when rubbing something. It needs some kind of external pressure to make it work – that’s the source of energy.

The idea goes as follows: a polymer layer is placed over metal; another movable metal surface then contacts the polymer on top so that, when in contact, you effectively have a polymer sandwich. In this configuration, the polymer accepts charge from the top metal, leaving a net positive charge in the metal. The metal layer is then moved away from the polymer.

The two metal layers are connected through a resistor. So now, because that top metal layer has moved out of range, the negative charges move towards the lower metal layer, and the excess charges on the top metal rush from the top metal layer, through the resistor – doing work – to the bottom layer.

This process is repeated, and the charges travel back up to the top layer when it comes in contact again.


The physical implementation of this involved small polydimethylsiloxane (PDMS) pyramids that would get squished by the top metal sliver contact. The size of the pyramids matters – smaller ones give more surface area and therefore a higher voltage, and they’re more sensitive. Larger ones, on the other hand, can handle a wider range of pressure because the pressure “saturates” at a higher level (the bigger pyramids have a higher restoring force).Pyramids.png

They were able to extract hundreds of µW/cm2 – enough to run, for example, some kind of implantable device. Of course, you need a source of motion – either vibration or… makes me wonder if the periodic pressure in the blood could be harvested.

If you have the IEDM proceedings, you can find all the details in papers 8.2 and 8.3.


(All images courtesy IEDM.)

Leave a Reply

featured blogs
Sep 16, 2021
I was quite happy with the static platform I'd created for my pseudo robot heads, and then some mad impetuous fool suggested servos. Oh no! Here we go again......
Sep 16, 2021
CadenceLIVE, Cadence's annual user conference, has been a great platform for Cadence technology users, developers, and industry experts to connect, share ideas and best practices solve design... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Sep 15, 2021
Learn how chiplets form the basis of multi-die HPC processor architectures, fueling modern HPC applications and scaling performance & power beyond Moore's Law. The post What's Driving the Demand for Chiplets? appeared first on From Silicon To Software....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Accurate Full-System Thermal 3D Analysis

Sponsored by Cadence Design Systems

Designing electronics for the data center challenges designers to minimize and dissipate heat. Electrothermal co-simulation requires system components to be accurately modeled and analyzed. Learn about a true 3D solution that offers full system scalability with 3D analysis accuracy for the entire chip, package, board, and enclosure.

Click here for more information about Celsius Thermal Solver

featured paper

Configure the charge and discharge current separately in a reversible buck/boost regulator

Sponsored by Maxim Integrated (now part of Analog Devices)

The design of a front-end converter can be made less complicated when minimal extra current overhead is required for charging the supercapacitor. This application note explains how to configure the reversible buck/boost converter to achieve a lighter impact on the system during the charging phase. Setting the charge current requirement to the minimum amount keeps the discharge current availability intact.

Click to read more

featured chalk talk

Build, Deploy and Manage Your FPGA-based IoT Edge Applications

Sponsored by Mouser Electronics and Intel

Designing cloud-connected applications with FPGAs can be a daunting engineering challenge. But, new platforms promise to simplify the process and make cloud-connected IoT design easier than ever. In this episode of Chalk Talk, Amelia Dalton chats with Tak Ikushima of Intel about how a collaboration between Microsoft and Intel is pushing innovation forward with a new FPGA Cloud Connectivity Kit.

Click here for more information about Terasic Technologies FPGA Cloud Connectivity Kit