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Shootout at the FinFET Corral

It’s high noon at IEDM. Both Intel and IBM have “late-breaking news” with their 14-nm FinFET numbers. The giant room is filled to bursting capacity. I’m lucky enough to have some space along the side wall, far from the screen. So far, in fact, that much of what’s on the screen is completely illegible.

Oh, and did I mention photography is not allowed? So… you can’t see the information, you can’t record it even if you saw it… you could busily write what little you can see but then you’re not listening… Oh well, the paper is in the proceedings and I should be able to get the slides after the fact. Right?

Nope. IBM politely declined. Intel didn’t respond at all. (Good thing the proceedings have contact information…) So if the paper is the only record of what happened, then why bother with the presentation? Except for those in the center of the room…

Yeah, I was frustrated, since, in these presentations, you can get a better sense of context and perspective, but only if you have a photographic memory. And I don’t. (And getting less so with each day.) There were definitely points that were made in the presentations that are not in the paper… so I can’t report them.

The whole deal here is Intel’s 14-nm bulk-silicon process vs. IBM’s 14-nm SOI process. And here’s the major takeaway: cost and performance have improved. Moore’s Law, reported as dead at the leading nodes, has taken a few more breaths. It’s just like the good old days, where area shrunk enough to make up for increased costs, and performance gained substantially.

I was going to compare some numbers here, but it’s too spotty to find numbers that they both reported in their papers. For instance, IBM reports a 35% performance improvement over 22 nm; as far as I can tell, Intel reported a performance improvement in the presentation, but didn’t put it in the paper. (I assume that’s intentional.)

Some notable process points:

  • IBM
    • Has a dual-work-function process that allows optimizing both low- and high-VT devices without resorting to doping. No details provided on that process.
    • 15 layers of copper
    • Includes deep-trench embedded DRAM.
  • Intel
    • Uses sub-fin doping.
    • Fin is now much more rectangular than their last edition.
    • 13 interconnect layers
    • They use air-gapped interconnects: pockets of air between lines on select metal layers that reduce capacitance by 17%. They were not willing to discuss how they do the air-gapping, just that they do.
    • Their random variation for VT, which grew from node to node for many nodes, is almost down to where it was at the 90-nm node.

Select images data follow…

[Suggestion to IEDM: require that presentations be made available. They shouldn’t be presenting material if they don’t have the cojones to stand behind it after the presentation…]

Cross-sections:

IBM:

IBM_photo.png

Intel:

Intel_photo.png

 

Pitches:

IBM:

 IBM_table.png

 Intel:

Intel_table.png


Transistor performance:

IBM:

IBM_xstor.png

Intel:

Intel_xstor.png

All images courtesy IEDM.

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