editor's blog
Subscribe Now

Shootout at the FinFET Corral

It’s high noon at IEDM. Both Intel and IBM have “late-breaking news” with their 14-nm FinFET numbers. The giant room is filled to bursting capacity. I’m lucky enough to have some space along the side wall, far from the screen. So far, in fact, that much of what’s on the screen is completely illegible.

Oh, and did I mention photography is not allowed? So… you can’t see the information, you can’t record it even if you saw it… you could busily write what little you can see but then you’re not listening… Oh well, the paper is in the proceedings and I should be able to get the slides after the fact. Right?

Nope. IBM politely declined. Intel didn’t respond at all. (Good thing the proceedings have contact information…) So if the paper is the only record of what happened, then why bother with the presentation? Except for those in the center of the room…

Yeah, I was frustrated, since, in these presentations, you can get a better sense of context and perspective, but only if you have a photographic memory. And I don’t. (And getting less so with each day.) There were definitely points that were made in the presentations that are not in the paper… so I can’t report them.

The whole deal here is Intel’s 14-nm bulk-silicon process vs. IBM’s 14-nm SOI process. And here’s the major takeaway: cost and performance have improved. Moore’s Law, reported as dead at the leading nodes, has taken a few more breaths. It’s just like the good old days, where area shrunk enough to make up for increased costs, and performance gained substantially.

I was going to compare some numbers here, but it’s too spotty to find numbers that they both reported in their papers. For instance, IBM reports a 35% performance improvement over 22 nm; as far as I can tell, Intel reported a performance improvement in the presentation, but didn’t put it in the paper. (I assume that’s intentional.)

Some notable process points:

  • IBM
    • Has a dual-work-function process that allows optimizing both low- and high-VT devices without resorting to doping. No details provided on that process.
    • 15 layers of copper
    • Includes deep-trench embedded DRAM.
  • Intel
    • Uses sub-fin doping.
    • Fin is now much more rectangular than their last edition.
    • 13 interconnect layers
    • They use air-gapped interconnects: pockets of air between lines on select metal layers that reduce capacitance by 17%. They were not willing to discuss how they do the air-gapping, just that they do.
    • Their random variation for VT, which grew from node to node for many nodes, is almost down to where it was at the 90-nm node.

Select images data follow…

[Suggestion to IEDM: require that presentations be made available. They shouldn’t be presenting material if they don’t have the cojones to stand behind it after the presentation…]

Cross-sections:

IBM:

IBM_photo.png

Intel:

Intel_photo.png

 

Pitches:

IBM:

 IBM_table.png

 Intel:

Intel_table.png


Transistor performance:

IBM:

IBM_xstor.png

Intel:

Intel_xstor.png

All images courtesy IEDM.

Leave a Reply

featured blogs
Jan 27, 2021
Here at the Cadence Academic Network, it is always important to highlight the great work being done by professors, and academia as a whole. Now that AWR software solutions is a part of Cadence, we... [[ Click on the title to access the full blog on the Cadence Community site...
Jan 27, 2021
Super-size. Add-on. Extra. More. We see terms like these a lot, whether at the drive through or shopping online. There'€™s always something else you can add to your order or put in your cart '€“ and usually at an additional cost. Fairly certain at this point most of us kn...
Jan 27, 2021
Cloud computing security starts at hyperscale data centers; learn how embedded IDE modules protect data across interfaces including PCIe 5.0 and CXL 2.0. The post Keeping Hyperscale Data Centers Safe from Security Threats appeared first on From Silicon To Software....
Jan 25, 2021
In which we meet the Photomath calculator, which works with photos of your equations, and the MyScript calculator, which allows you to draw equations with your finger....

featured paper

Overcoming Signal Integrity Challenges of 112G Connections on PCB

Sponsored by Cadence Design Systems

One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).

Click here to download the whitepaper

Featured Chalk Talk

Rail Data Connectivity

Sponsored by Mouser Electronics and TE Connectivity

The rail industry is undergoing a technological revolution right now, and Ethernet connectivity is at the heart of it. But, finding the right interconnect solutions for high-reliability applications such as rail isn’t easy. In this episode of Chalk Talk, Amelia Dalton chats with Egbert Stellinga from TE Connectivity about TE’s portfolio of interconnect solutions for rail and other reliability-critical applications.

Click here for more information about TE Connectivity EN50155 Managed Ethernet Switches