editor's blog
Subscribe Now

New Nanoimprint from EVG

With all the delicacy involved in the advanced lithography techniques we use for patterning exquisitely small features onto wafers, occasionally we come back to a brute-force approach: nanoimprint lithography (NIL). Instead of painstakingly exposing patterns onto a photoresist, we simply press a patterned die (PS this is the kind of die whose plural is “dies,” not the singulated silicon bits whose plural is “dice”) into a bed of moosh to create a pattern as if making an old-school vinyl record. Harden the material, and we’re good.

While already used for hard drives, we’ve also seen it combined with DSA for even more aggressive hard drives. But that’s all still research stuff.

EVG_NIL_photo.jpgEVG recently announced a high-volume production SmartNIL process. It’s a UV-cured approach, although any of you wondering why they get to use UV while EUV is stuck at the starting gate have no reason to be jealous. Unlike EUV, you don’t need a carefully collimated beam of UV. You can just bathe your wafer in incoherent swaths of UV light.

The obvious question then might be, why can’t I use this? And the answer is, maybe you can! From a target-technology standpoint, your odds are good. (From a number-of-designers standpoint, not so much). It’s easier to answer the question, “What can’t this be used for?” than, “What can it be used for?”

The answer to the easier question is, “Transistors.” There are two issues with NIL for advanced transistors: feature size and defectivity.

  • Yes, according to EVG’s Gerald Kreindl, advanced research work in John Rogers’ group at Illinois has actually replicated a carbon nanotube (CNT) using imprint. (Which is interesting since a CNT is a 3D feature…) The point being, there’s not a fundamental limit to feature size. (OK, there is, but I don’t think anyone is going to try to replicate a quark using NIL) Realistically speaking, SmartNIL is for features in the 20-100-nm (or bigger) range (more like 40 and up in high volume). That would leave out fins, for example.
  • The other issue is defectivity: a slight glitch in a microfluidics channel isn’t going to cause any pain. That same glitch in a transistor may send valuable electrons in the wrong direction.

So if transistors are out, what does that leave? Lots: Optics, photonics,  LEDs, bioelectronics…

You can find out more in their announcement.

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Unique AMS Emulation Technology

Sponsored by Synopsys

Learn about Synopsys' collaboration with DARPA and other partners to develop a one-of-a-kind, high-performance AMS silicon verification capability. Please watch the video interview or read it online.

Read the interview online:

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Expanding SiliconMAX SLM to In-Field

Sponsored by Synopsys

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

Click here for more information about SiliconMAX Silicon Lifecycle Management