editor's blog
Subscribe Now

Wireless Power: Making Actual Product

2014-11-17_10_15_45-PowerSquare.png

Things have been a bit quiet on the wireless power front, but occasionally I’ll become aware of a new player and will dig in to find out how they work. In particular, given that there are now two main competing resonant (e-field) charging standards, it’s interesting to learn where the various players stand.

As a quick review, the two standards are Qi, at a lower frequency (200 kHz) building off of its existing inductive charging market, and Rezence, at a higher frequency (6.78 MHz), which is a newcomer.

The latest company I ran across was PowerSquare, who announced their technology this past summer. These guys help illustrate how this market is playing out. Some companies, like WiTricity, are firmly allied with a standard (in their case,

Rezence). They develop the basic technology and then license it to companies building actual charging stations. Most of the companies and standards groups I’ve talked with in the past were of this variety.

PowerSquare is not: they’re in the next tier of companies trying to establish a retail brand. As such, their focus isn’t on evangelizing one or another technology; their focus is on selling chargers. So PowerSquare isn’t allied with one or the other approach; they’re going to use what’s available and what works and what’s cost effective.

In this case, their current products leverage the Qi standard. Why? Because that’s what’s there now. In fact, they’re not even doing the newer e-field resonant thing – that’s not ready yet (or wasn’t when they assembled their product). So they use the old inductive (m-field-oriented) approach.

They have, however, adopted some of the techniques we’ve discussed before, creating a pad with an array of coils so that you can put a phone anywhere on it or charge multiple phones at once. So, while they get “x” and “y” positioning flexibility, what they don’t get with that approach is increased “z” spacing: the phone still has to be on the pad, close to the coils. You can’t mount the pad under a table or counter – the resonant approach would be needed for that.

Looking forward, PowerSquare CEO Pavan Pudipeddi sees plusses and minuses for both evolving standards. The biggest thing Qi has going for it is momentum: its legacy helps propel it forward. They already have working technology, albeit inductive, so, even though they’re getting their resonant approach squared away, there’s less pressure because they’ve already got something to sell.

That legacy is also a challenge for Qi, because they’re all about backward-compatibility. So decisions from the past affect the future; that could feel like baggage at some point.

Rezence, on the other hand, has in its favor support from some heavy-hitting companies: Intel, Samsung, and Qualcomm among them. Their challenge is that this technology is new, and there’s intense pressure to get product out the door to establish some traction. In particular, Mr. Pudipeddi wasn’t aware of any uptake of the Rezence technology in phone designs as of when we spoke. (That could have changed by now.)

The first Rezence-based product is expected by the end of the year, however, so the battle will be fully joined at that point. And PowerSquare will continue to use whichever versions of whichever technology hold the most promise for selling units at the retail level.

You can read PowerSquare’s technology announcement here.

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

How to Harness the Massive Amounts of Design Data Generated with Every Project

Sponsored by Cadence Design Systems

Long gone are the days where engineers imported text-based reports into spreadsheets and sorted the columns to extract useful information. Introducing the Cadence Joint Enterprise Data and AI (JedAI) platform created from the ground up for EDA data such as waveforms, workflows, RTL netlists, and more. Using Cadence JedAI, engineering teams can visualize the data and trends and implement practical design strategies across the entire SoC design for improved productivity and quality of results.

Learn More

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

"Scalable Power Delivery" for High-Performance ASICs, SoCs, and xPUs

Sponsored by Infineon

Today’s AI and Networking applications are driving an exponential increase in compute power. When it comes to scaling power for these kinds of applications with next generation chipsets, we need to keep in mind package size constraints, dynamic current balancing, and output capacitance. In this episode of Chalk Talk, Mark Rodrigues from Infineon joins Amelia Dalton to discuss the system design challenges with increasing power density for next generation chipsets, the benefits that phase paralleling brings to the table, and why Infineon’s best in class transient performance with XDP architecture and Trans Inductor Voltage Regulator can help power  your next high performance ASIC, SoC or xPU design.

Click here for more information about computing and data storage from Infineon