editor's blog
Subscribe Now

Turning InGaAs on its Head

InGaAs is one of the new wunderkind semiconductors, favored for high-electron-mobility transistors (HEMTs) and for optical designs (more about that in a future post). But, as with other more exotic materials, it isn’t silicon, and therefore it doesn’t benefit from silicon’s economics.

The problem is the lattice: to grow single-crystal stress-free InGaAs, you have to use a substrate with a similar lattice (you have some flexibility by adjusting the quantity of indium, which tweaks the lattice). Three III/V substrates available are GaAs, InAs, and InP, the latter of which is more typical. None of them is silicon.

Let’s say you want a semiconductor-over-insulator configuration using InGaAs instead of silicon (InGaAs-oI instead of SoI). You want a thin layer of pure InGaAs with an abrupt stop at the oxide. How are you going to do that?

A team from the University of Tokyo, JST-CREST, and IntelliEPI came up with a wafer-bonding approach that uses only silicon substrates. The main difference from a traditional SoI wafer (well, aside from the InGaAs) is that the buried oxide (BOX) isn’t SiO2; it’s Al2O3.

The approach starts with the “donor” wafer, growing inGaAs on silicon. But… you can’t do that directly because of the lattice issue. So they laid down a couple “buffer” layers instead to ease between the  lattices and keep the stresses low enough to allow single-crystal InGaAs to grow: GaAs, followed by InAlAs, topped with a layer of InGaAs.

A layer of oxide – Al2O3 – was then laid over the top. Yeah, you’ve pretty much got a bunch of layers of every combination of indium, gallium, arsenic, and aluminum in there.

Meanwhile, over on another silicon wafer, another layer of Al2O3 is laid down. The two oxide tops are polished, and then they are mated face-to-face. And all of the layers of the donor wafer except the InGaAs are etched away. What you’re left with is a top layer of InGaAs ending abruptly at the BOX edge. No mamby-pamby buffer layers left.

InGaAs_figure_525.png

 

Electron mobility in the resulting layer was 1700 cm2/V, indicating low defectivity and high quality.

Note that the economics here come not just from the silicon material per se, but also from the fact that this provides a scaling path to 300-mm wafers, which aren’t available for more exotic substrates.

You can find their report (behind a paywall) here.

A separate team from UC San Diego, Nanyang Technological University in Singapore, and Los Alamos Labs also did some InGaAs work to deal with effective wafer flipping and bonding, published earlier this year. They used NiSi to effect the bonding. Their BOX layer was SiO2 (with a thin HfO2 buffer to the InGaAs layer). But, critically, the donor wafer was InP, not silicon.

You can find that full report here.

Leave a Reply

featured blogs
Feb 24, 2021
mmWave applications are all the rage. Why? Simply put, the 5G tidal wave is coming. Also, ADAS systems use 24 GHz for SRR applications and 77 GHz for LRR applications. Obviously, the world needs mmWave tech! Traditional mmWave technology spans the frequency range of 30 –...
Feb 24, 2021
Crowbits are programmable, LEGO-compatible, magnetically-coupled electronic blocks to interest kids in electronics and computing and facilitate their STEM activities....
Feb 24, 2021
With DVCon 2021 on the horizon we share a primer on our datapath verification technology HECTOR, exploring its impact on machine learning & AI chip design. The post Why Datapath Validation Is Important'€”and How HECTOR Technology Can Help appeared first on From Silico...
Feb 24, 2021
When I worked for Cadence back in the early oughts, we developed a layout database called OpenAccess, usually abbreviated to OA. It had actually been designed from the ground up to be the native... [[ Click on the title to access the full blog on the Cadence Community site. ...

featured video

Designing your own Processor with ASIP Designer

Sponsored by Synopsys

Designing your own processor is time-consuming and resource intensive, and it used to be limited to a few experts. But Synopsys’ ASIP Designer tool allows you to design your own specialized processor within your deadline and budget. Watch this video to learn more.

Click here for more information

featured paper

Using the DS28E18, The Basics

Sponsored by Maxim Integrated

This application note goes over the basics of using the DS28E18 1-Wire® to I2C/SPI Bridge with Command Sequencer and discusses the steps to get it up and running quickly. It then shows how to use the device with two different devices. The first device is an I2C humidity/temperature sensor and the second one is an SPI temperature sensor device. It concludes with detailed logs of each command.

Click here to download the whitepaper

Featured Chalk Talk

Electrification of the Vehicle

Sponsored by Mouser Electronics and KEMET

The automotive technology revolution has arrived, and with it - new demands on components for automotive applications. Electric vehicles, ADAS, connected cars, and autonomous driving put fresh demands on our electrical and electronic parts. In this episode of Chalk Talk, Amelia Dalton chats with Nick Stephen of KEMET about components for the next generation of automobiles.

More information about KEMET Electronics ALA7D & ALA8D Snap-In Capacitors