editor's blog
Subscribe Now

Faster Extraction from Cadence

Cadence recently announced new extraction tools, claiming both greater speed (5x) and best-in-class accuracy for full-chip extraction. And what is it that lets them speed up without sacrificing results?

The answer is the same thing that has benefited so many EDA tools over the last few years: parallelism. Both within a box (multi-threading) and using multiple boxes (distributed computing). The tools can scale up to hundreds of CPUs, although they’re remaining mum on the details of how they did this…

They have two new tools:  a new random-walk field solver (Quantus FS) and the full-chip extraction tool (Quantus QRC). They say that the field solver is actually running around 20 times faster than their old one.

The field solver is much more detailed and accurate than the full-chip extraction tool. It’s intended for small circuits and high precision; its results are abstracted for use on a larger scale by the full-chip tool. That said, they claim good correlation between QRC and FS, so not much is lost in the abstraction.

They’ve also simplified the FinFET model, cutting the size of the circuit in half and increasing analysis speed by 2.5x.

While QRC is intended for the entire chip, it can also be used incrementally – in which case it can be three times again as fast. Both the Encounter digital implementation tool and their Tempus timing analysis tool can take advantage of this incremental capability to do real-time extraction as the tools make decisions. It’s also integrated into the Virtuoso analog/custom tool.

As to accuracy, they say they meet all of TSMC’s golden FinFET data, that they achieve consistent results with single- and multi-corner analysis, and that they’ve been certified by TSMC for the 16-nm node.

Their fundamental capabilities are summarized in the following figure, although this coverage is consistent with the prior tools.

QRC_functions_500.png

Image courtesy Cadence

You can read more in their announcement.

Leave a Reply

featured blogs
Jul 11, 2025
Can you help me track down the source of the poem titled 'The African Tigger is Fading Away'?...

Libby's Lab

Libby's Lab - Scopes out Littelfuse C&K Aerospace AeroSplice Connectors

Sponsored by Mouser Electronics and Littelfuse

Join Libby and Demo in this episode of “Libby’s Lab” as they explore the Littelfuse C&K Aerospace Aerosplice Connectors, available at Mouser.com! These connectors are ideal for high-reliability easy-to-use wire-to-wire connections in aerospace applications. Keep your circuits charged and your ideas sparking!

Click here for more information

featured paper

AI-based Defect Detection System that is Both High Performance and Highly Accurate Implemented in Low-cost, Low-power FPGAs

Sponsored by Altera

Learn how MAX® 10 FPGAs enable real-time, high-accuracy AI-based defect detection at the industrial edge without a GPU. This white paper explores a production-proven solution that delivers 24× higher accuracy, 488× lower latency, and 20× lower power than traditional approaches, with a compact footprint ideal for embedded vision systems.

Click to read more

featured chalk talk

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
Sponsored by Synopsys
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
257,126 views