editor's blog
Subscribe Now

IC Compiler Reinvented

What if you could just… toss it all and start over? (OK, maybe all except the router?)

If you’re Synopsys, you now know: you’d end up with IC Compiler II.

They’ve had a good ride with IC Compiler, and they continue to ride that. But things have changed a lot since it appeared on the scene. Requirements and expectations have mushroomed, and they’ve done a lot of new research and acquired a lot of technology (apparently their Magma acquisition fed into this). And so they’ve pretty much replaced everything in IC Compiler except the router.

The new approach pushes planning to a much earlier stage. Engines have been completely redone, with an emphasis on the ability to use multiple processors, which means that more options can be explored. They use that magic number “10x” for many of the speedups. Not only that, but their optimization engines are better at finding a global optimum in an analytical fashion rather than via the alternative: generating a bazillion options and picking the best one.

More specifically, they address the following areas:

  • Infrastructure
    • Hierarchy is handled natively.
    • They have a new timer and extractor that are used consistently throughout.
    • They can deal with incomplete data early in the design cycle.
    • They’ve implemented an integrated library and management approach.
  • Planning
    • They’ve implemented adaptive abstraction and modeling.
    • They support transparent multiple instances.
    • What-if analysis can be done in real time instead of having to compile.
    • A floorplan can be automatically synthesized.
  • Implementation
    • This is where they have the new multi-threaded optimization engine that analytically finds global optima.
    • They’ve redone their multi-corner, multi-mode, multi-voltage handling.
    • Placement and clock optimization now happen in a single step.
    • They’ve completely redone the clock tree synthesis engine.
    • They’ve put in place new ways to achieve closure after routing.

ICC_II_Graphic_Press2_red.jpg

At this point, the entire new system isn’t in place yet. They’ve got bits and pieces that they’ve been feeding to a few lead customers to refine things as they approach a mid-year full release.

They will continue to support the original IC Compiler well into the future. They see a gradual shift from one to the other; they’re not going to pull a Microsoft and force everyone over.

You can check out more in their announcement.

Leave a Reply

featured blogs
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

TDK CLT32 power inductors for ADAS and AD power management

Sponsored by TDK

Review the top 3 FAQs (Frequently Asked Questions) regarding TDK’s CLT32 power inductors. Learn why these tiny power inductors address the most demanding reliability challenges of ADAS and AD power management.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

What are the Differences Between an Integrated ADC and a Standalone ADC?
Sponsored by Mouser Electronics and Microchip
Many designs today require some form of analog to digital conversion but how you implement an ADC into your design can make a big difference when it comes to accuracy and precision. In this episode of Chalk Talk, Iman Chalabi from Microchip and Amelia Dalton investigate the benefits of both integrated ADC solutions and standalone ADCs. They discuss the roles that internal switching noise, process technology, and design complexity play when choosing the right ADC solution for your next design.
Apr 17, 2023
27,242 views