editor's blog
Subscribe Now

IC Compiler Reinvented

What if you could just… toss it all and start over? (OK, maybe all except the router?)

If you’re Synopsys, you now know: you’d end up with IC Compiler II.

They’ve had a good ride with IC Compiler, and they continue to ride that. But things have changed a lot since it appeared on the scene. Requirements and expectations have mushroomed, and they’ve done a lot of new research and acquired a lot of technology (apparently their Magma acquisition fed into this). And so they’ve pretty much replaced everything in IC Compiler except the router.

The new approach pushes planning to a much earlier stage. Engines have been completely redone, with an emphasis on the ability to use multiple processors, which means that more options can be explored. They use that magic number “10x” for many of the speedups. Not only that, but their optimization engines are better at finding a global optimum in an analytical fashion rather than via the alternative: generating a bazillion options and picking the best one.

More specifically, they address the following areas:

  • Infrastructure
    • Hierarchy is handled natively.
    • They have a new timer and extractor that are used consistently throughout.
    • They can deal with incomplete data early in the design cycle.
    • They’ve implemented an integrated library and management approach.
  • Planning
    • They’ve implemented adaptive abstraction and modeling.
    • They support transparent multiple instances.
    • What-if analysis can be done in real time instead of having to compile.
    • A floorplan can be automatically synthesized.
  • Implementation
    • This is where they have the new multi-threaded optimization engine that analytically finds global optima.
    • They’ve redone their multi-corner, multi-mode, multi-voltage handling.
    • Placement and clock optimization now happen in a single step.
    • They’ve completely redone the clock tree synthesis engine.
    • They’ve put in place new ways to achieve closure after routing.

ICC_II_Graphic_Press2_red.jpg

At this point, the entire new system isn’t in place yet. They’ve got bits and pieces that they’ve been feeding to a few lead customers to refine things as they approach a mid-year full release.

They will continue to support the original IC Compiler well into the future. They see a gradual shift from one to the other; they’re not going to pull a Microsoft and force everyone over.

You can check out more in their announcement.

Leave a Reply

featured blogs
Dec 1, 2022
Raspberry Pi are known for providing lost-cost computing around the world. Their computers have been used by schools, small businesses, and even government call centers. One of their missions is to educate children about computers and to help them realize their potential thro...
Nov 30, 2022
By Chris Clark, Senior Manager, Synopsys Automotive Group The post How Software-Defined Vehicles Expand the Automotive Revenue Stream appeared first on From Silicon To Software....
Nov 30, 2022
By Joe Davis Sponsored by France's ElectroniqueS magazine, the Electrons d'Or Award program identifies the most innovative products of the… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

How to Harness the Massive Amounts of Design Data Generated with Every Project

Sponsored by Cadence Design Systems

Long gone are the days where engineers imported text-based reports into spreadsheets and sorted the columns to extract useful information. Introducing the Cadence Joint Enterprise Data and AI (JedAI) platform created from the ground up for EDA data such as waveforms, workflows, RTL netlists, and more. Using Cadence JedAI, engineering teams can visualize the data and trends and implement practical design strategies across the entire SoC design for improved productivity and quality of results.

Learn More

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Reduce Power System Needs with Multichannel Power Monitors

Sponsored by Mouser Electronics and Microchip

Power monitors can be very effective in terms of power management for a variety of designs and the use of a multichannel power monitors can not only lower your overall system power but also lower your code overhead, simplify prototyping and event detection. In this episode of Chalk Talk, Amelia Dalton chats with Mitch Polonsky from Microchip about the benefits of multichannel power monitors and how Microchip’s PAC194x and PAC195x can help you monitor your power in your next design.

Click here for more information about Microchip Technology PAC194x & PAC195x Monitors