editor's blog
Subscribe Now

A Jump in EUV Resist Sensitivity

There was an interesting presentation that happened towards the end of SPIE Litho – it seemed to catch the audience off guard, and I frankly went away with the sense that there was some confusion in the room.

The presentation discussed an experiment that was done at Osaka University as part of the overall effort to optimize EUV exposure. It all relates to this seemingly inviolate triumvirate of “RLS”: resolution, LWR (line-width roughness), and sensitivity. Improvements within these three have to come at the expense of something within these three – they form a zero-sum game.

Normally, you expose the photoresist through the mask for the entire length of the exposure. The photons create acid where they interact with the resist, and this acid provides for the selective removal of resist material during development.

This experiment changed that. The exposure was broken into two steps:

  • A short exposure through the mask
  • After 10-15 minutes, then, with no mask, just a flood of UV across the entire wafer.

The first exposure seemed to create some acid, but mostly “sensitized” the photoresist (and I frankly didn’t come away understanding what that “sensitizing” meant from a chemical standpoint). The strange thing then was that flooding with the second exposure created the normal amount of acid only in the sensitized area.

This provided about 9 times the prior sensitivity, with no apparent tradeoff in LWR or resolution.

Note that no special resists were used; these were the same resists as are currently being used.

I didn’t get the sense that they had a real handle on what the underlying mechanisms were, and it was surprising to the audience. Assuming the data are correct, it’s certainly an interesting result. We’ll have to see if anything further comes of it, or if it goes the way of cold fusion…

Leave a Reply

featured blogs
Apr 18, 2021
https://youtu.be/afv9_fRCrq8 Made at Target Oakridge (camera Ziyue Zhang) Monday: "Targeting" the Open Compute Project Tuesday: NUMECA, Computational Fluid Dynamics...and the America's... [[ Click on the title to access the full blog on the Cadence Community s...
Apr 16, 2021
Spring is in the air and summer is just around the corner. It is time to get out the Old Farmers Almanac and check on the planting schedule as you plan out your garden.  If you are unfamiliar with a Farmers Almanac, it is a publication containing weather forecasts, plantin...
Apr 15, 2021
Explore the history of FPGA prototyping in the SoC design/verification process and learn about HAPS-100, a new prototyping system for complex AI & HPC SoCs. The post Scaling FPGA-Based Prototyping to Meet Verification Demands of Complex SoCs appeared first on From Silic...
Apr 14, 2021
By Simon Favre If you're not using critical area analysis and design for manufacturing to… The post DFM: Still a really good thing to do! appeared first on Design with Calibre....

featured video

The Verification World We Know is About to be Revolutionized

Sponsored by Cadence Design Systems

Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.

Click here for more information

featured paper

Understanding the Foundations of Quiescent Current in Linear Power Systems

Sponsored by Texas Instruments

Minimizing power consumption is an important design consideration, especially in battery-powered systems that utilize linear regulators or low-dropout regulators (LDOs). Read this new whitepaper to learn the fundamentals of IQ in linear-power systems, how to predict behavior in dropout conditions, and maintain minimal disturbance during the load transient response.

Click here to download the whitepaper

featured chalk talk

Fundamentals of ESD/TVS Protection

Sponsored by Mouser Electronics and Nexperia

ESD protection is a critical, and often overlooked design consideration in many of today’s systems. There is a wide variety of solutions available for ESD protection, and choosing the right one for your design can be a daunting and confusing task. In this episode of Chalk Talk, Amelia Dalton chats with Tom Wolf of Nexperia about choosing the right ESD protection for your next design.

Click here for more information about Nexperia PCMFxUSB3B/C - CMF EMI filters with ESD Protection