editor's blog
Subscribe Now

More Common-Process MEMS

Last year we took a look at a couple of proposals for universal processes from Teledyne/DALSA and CEA-Leti that could be used to make many different MEMS elements, trying to move past the “one product, one process” trap. We’ve also reported on the AMFitzgerald/Silex modular approach and their first device.

Well, the first design using CEA-Leti’s M&NEMS process has rolled out: a single MEMS chip with three accelerometers and three gyroscopes designed and implemented by Tronics. They’re not quite the smallest of the 6-DOF sensors, but they claim that, with more optimization, they will be. Right now their die size is 4 mm2. And they say that all main parameters are on track with their simulation models.

But this is just the first functional version; they’re going back to work some more while, at the same time, giving it a companion ASIC, releasing them at the end of this year.

They’re also using the same process to create a 9-DOF sensor set, with all of the sensors on a single MEMS chip. Also for release at the end of the year. And, the idea is, that, if they wanted to, they could also include a pressure sensor and a microphone, since they can all presumably be made on this same process. Yeah, you might wonder whether integrating a microphone with those other sensors has value; even if it doesn’t, being able to make it separately using the same process as the n-DOF chip still brings a huge level of manufacturing simplification.

These efforts, if successful, could represent a fresh breath of efficiency for some of the oldest sensors in the MEMS world. The industry also has new MEMS elements in the works, like gas sensors and such. If a standard process like this could be used for new sensors as well, then at some point new sensors could launch on standard processes rather than having to do the “one process” thing first like accelerometers and their ilk have done.

There are those who believe that these standard processes are too restrictive to allow the design of sensors with arbitrary characteristics. We’ll continue to keep an eye on this stuff to see whether these common-process skeptics can eventually be appeased or whether they’ll be proven correct.

Check out the details in Tronics’s release.

Leave a Reply

featured blogs
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
Using the bitwise operators in general -- and employing them to perform masking, bit testing, and bit setting/clearing operations in particular -- can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

Featured Video

Product Update: DesignWare® Foundation IP

Sponsored by Synopsys

Join Prasad Saggurti for an update on Synopsys’ DesignWare Foundation IP, including the world’s fastest TCAMs, widest-voltage GPIOs, I2C & I3C IOs, and LVDS IOs. Synopsys Foundation IP is silicon-proven in 7nm in more than 500,000 customer wafers, and 5nm is in development.

Click here for more information about DesignWare Foundation IP: Embedded Memories, Logic Libraries & GPIO

Featured Paper

Cryptography: How It Helps in Our Digital World

Sponsored by Maxim Integrated

Gain a basic understanding of how cryptography works and how cryptography can help you protect your designs from security threats.

Click here to download the whitepaper

Featured Chalk Talk

TensorFlow to RTL with High-Level Synthesis

Sponsored by Cadence Design Systems

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

More information