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Speed Sensors in Chips

One of the immense challenges of aggressive-node design is coping with all of the variations both in the the silicon, given processing variability, and in the operating conditions. The approach has been to find ways to model the variation and create a design that is robust under all the various combinations. Not easy, since each chip comes out of the fab slightly different from its siblings.

And if you want to operate the chip over a wider range, you’ve just made the problem harder. In particular, for a circuit that will operate under a wide range of VDD values, it’s crazy hard to implement the design of a complex circuit and have that single design work under all conditions.

One of the ways of dealing with this has been dynamic voltage and frequency scaling (DVFS), but many approaches to this rely on a static mapping of temperatures, voltages, and frequencies such that, for a given temperature, there is a fixed setting that the circuit will move to.

ST and Leti used an even more dynamic approach, and one that arguably stops trying to characterize its way around the problem and, instead, ask each circuit when it’s about to go out of bounds. They did this for a DSP built on their ultra-thin body buried-oxide fully-depleted silicon-on-insulator (UTBB FD-SOI) process (yeah, that’s a mouthful).

The idea here is that, rather than designing for the various corners, they designed for typical case and then built sensors on the die to indicate when they needed to adjust voltage or frequency. They used two basic approaches, which they called CODA (ClOning DAta paths) and TMFLT (TiMing FauLT).

With CODA, they picked 16 representative critical paths and literally replicated them in pairs. One was a forward path, called a “canary” path (presumably because it’s an early indicator, like the famous canary in the coal mine). The path was then replicated in reverse so that it could be looped to oscillate; they could then measure that frequency directly. They issue a warning when the clock frequency gets to 1/(clone delay), and they correlate this through the frequency measured using the loop oscillation mode. They found that five of the pairs could predict the actual circuit fMAX within 3-4% with a 1-V supply.

The TMFLT circuits are quite different. They instrument 128 critical paths (although they may or may not be the most critical paths) with sensors that warn when slack time has decreased to 160 ps. They refer to these as TMFLT-S (S for “sensor”). While these can be activated by some pre-determined test pattern, they may not be activated during actual use. In other words, when conditions get tough (e.g., temperature heating up), you can’t necessarily rely on one of those paths just happening to be active so that it can warn you that timing is getting dicey.

So they created one more feature, a “programmable replica path” that doesn’t use any of the logic per se, but instead relies on a stored signature to set the delay. This is called TMFLT-R (R for “ring”). The way this signature is created is to run the TMFLT-S paths through the test pattern at, say, power-up. Power, frequency, and back bias are swept, finding the optimal points, and then measuring the corresponding TMFLT-R values and storing these signatures. During operation, the active frequency, voltage, and back bias can be measured, and the appropriate signature is used to set the TMFLT-R timing. So now TMFLT-R is acting as a proxy for all the TMFLT-S circuits, which may or may not be activated. Sounds complicated, but, at least at this very moment, I’ve convinced myself that it makes sense. (My brain’s relaxation constant is pretty quick, so all bets may be off in an hour.)

What’s interesting about these approaches is that they allow operating conditions to by dynamically altered not based on some static algorithm that was done at, say, characterization time, but by measuring what’s really going on in each individual circuit at any given time and looking for true indicators that performance is in danger.

They achieved a voltage range of 397 mV to 1.3 V. That’s more than a 1:3 range (compare that to old-school 4.5-V min circuits: the upper VDD would be, like, 13.5 V – which sounds crazy). fMAX was 460 MHz at the bottom end of the range and 2.6 GHz at the top end.

They talk about it in their release, and for those of you with ISSCC proceedings, you can get even more info in paper 27.1

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